ROM storage cell and method of fabrication

Abstract

A process and structure are disclosed for a programmable array for use in a read-only memory comprising diode elements and shorted diode elements. The elements are connected across bit and wordlines. The invention utilizes lateral polysilicon diodes and metal silicide layer bridging the junction of pre-selected diodes to short pre-selected diode elements. Programming is accomplished by either forming the silicide layer across the junctions of pre-selected diodes or removing the silicide layer from the junctions of pre-selected diodes.

What is claimed is: 
     
       1. A method comprising the steps of: forming a first insulating layer on a substrate;   forming a polysilicon layer on said first insulating layer;   patterning and etching said polysilicon layer into a plurality of polysilicon blocks;   doping a first region of each said polysilicon blocks with a first dopant type and doping a second abutting region of each said polysilicon blocks with a second dopant type whereby a junction region is formed;   depositing a layer of silicide forming metal;   removing said silicide forming metal from a predetermined area over preselected junction regions;   sintering to form a metallic silicide including removing unreacted portions of the silicide forming metal; and   forming a first conductive line connecting selected first regions of said polysilicon blocks and a second conductive line connecting selected second regions of said polysilicon blocks.   
     
     
       2. The method of claim 1, further comprising the step of forming a sidewall insulation on said polysilicon blocks. 
     
     
       3. The method of claim 1, wherein said first conductive line comprises polysilicon and is co-extensive with first doped regions of said polysilicon blocks. 
     
     
       4. The method of claim 1 wherein said silicide forming metal is selected from the group consisting of titanium, platinum, and tantalum. 
     
     
       5. A method comprising the steps of: forming a first insulating layer on a substrate;   forming a polysilicon layer on said first insulating layer;   patterning and etching said polysilicon layer into a plurality of polysilicon blocks;   doping a first region of each said polysilicon blocks with a first dopant type and doping a second abutting region of each said polysilicon blocks with a second dopant type whereby a junction region is formed;   depositing a layer of silicide forming metal;   sintering to form a metallic silicide including removing unreacted portions of the silicide forming metal; and   forming a first conductive line connecting selected first regions of said polysilicon blocks and a second conductive line connecting selected second regions of said polysilicon blocks.   
     
     
       6. The method of claim 5 further comprising the step of removing said silicide from a predetermined area over preselected junction regions. 
     
     
       7. The method of claim 5, further comprising the step of forming a sidewall insulation on said polysilicon blocks. 
     
     
       8. The method of claim 5, wherein said first conductive line comprises polysilicon and is co-extensive with said selected first regions of said polysilicon blocks. 
     
     
       9. The method of claim 5 wherein said silicide forming metal is selected from the group consisting of titanium, platinum, and tantalum. 
     
     
       10. The method of claim 5, wherein the step of removing said silicide is selected from the group consisting of etching, ion milling and laser ablation.