Polyload sram memory cell with low stanby current

Abstract

An SRAM cell formed on a semiconductor substrate with low standby current is disclosed. The memory cell includes a first inverter, a second inverter cross-coupled to the first inverter to form a storage element, a first load device coupled to the first inverter, a second load device coupled to the second inverter, a first access transistor coupled to an output port of the first inverter, and a second access transistor coupled to an output port of the second inverter. In this memory cell, the first load device is placed over the second inverter with substantial overlapping therebetween, so that resistance of the first load device increases when an input of the second inverter is at a low potential, thereby decreasing a standby current of the first load device. Similarly, the resistance of the second load device increases when an input of the first inverter is at a low potential.

What is claimed is: 
     
       1. A static random access memory cell formed on a semiconductor substrate, said memory cell comprising: a first inverter;   a second inverter cross-coupled to said first inverter to form a storage element;   a first load device, coupled to said first inverter, for pulling-up said first inverter to a power source;   a second load device, coupled to said second inverter, for pulling-up said second inverter to the power source;   a first access transistor coupled to an output port of said first inverter, so that stored data in the storage element is selectively communicated to a first bitline via said first access transistor, said selective communication through said first access transistor being controlled by a wordline; and   a second access transistor coupled to an output port of said second inverter, so that stored data in the storage element is selectively communicated to a second bitline via said second access transistor, said selective communication through said second access transistor being controlled by the wordline,   wherein said first load device is placed over said second inverter with substantial overlapping therebetween, when an input of said second inverter is at a low potential, a depletion region is generated between overlapped said first load device and said second inverter, obstructing movement of electrons in said first load device, thereby increasing resistance of said first load device and decreasing a standby current of said first load device, and   said second load device is placed over said first inverter with substantial overlapping therebetween, when an input of said first inverter is at a low potential, a depletion region is generated between overlapped said second load device and said first inverter, obstructing movement of electrons in said second load device, thereby increasing resistance of said second load device and decreasing a standby current of said second load device.   
     
     
       2. The memory cell according to claim 1, wherein said first inverter comprises an NMOS transistor. 
     
     
       3. The memory cell according to claim 1, wherein said second inverter comprises an NMOS transistor. 
     
     
       4. The memory cell according to claim 1, wherein said first load device comprises a polysilicon resistor. 
     
     
       5. The memory cell according to claim 1, wherein said second load device comprises a polysilicon resistor. 
     
     
       6. The memory cell according to claim 1, wherein said first access transistor comprises an NMOS transistor. 
     
     
       7. The memory cell according to claim 1, wherein said second access transistor comprises an NMOS transistor. 
     
     
       8. A static random access memory cell formed on a semiconductor substrate, said memory cell comprising: a first inverter;   a second inverter cross-coupled to said first inverter to form a storage element;   a first load device, coupled to said first inverter, for pulling-up said first inverter to a power source;   a second load device, coupled to said second inverter, for pulling-up said second inverter to the power source;   a first access transistor coupled to an output port of said first inverter, so that stored data in the storage element is selectively communicated to a first bitline via said first access transistor, said selective communication through said first access transistor being controlled by a wordline; and   a second access transistor coupled to an output port of said second inverter, so that stored data in the storage element is selectively communicated to a second bitline via said second access transistor, said selective communication through said second access transistor being controlled by the wordline,   wherein said first load device is placed over said second inverter with substantial overlapping therebetween, and said second load device is placed over said first inverter with substantial overlapping therebetween, and   said first load device being isolated from said second inverter only by dielectric material, and said second load device being isolated from said first inverter only by dielectric material.   
     
     
       9. The memory cell according to claim 8, wherein said first inverter comprises an NMOS transistor. 
     
     
       10. The memory cell according to claim 8, wherein said second inverter comprises an NMOS transistor. 
     
     
       11. The memory cell according to claim 8, wherein said first load device comprises a polysilicon resistor. 
     
     
       12. The memory cell according to claim 8, wherein said second load device comprises a polysilicon resistor. 
     
     
       13. The memory cell according to claim 8, wherein said first access transistor comprises an NMOS transistor. 
     
     
       14. The memory cell according to claim 8, wherein said second access transistor comprises an NMOS transistor. 
     
     
       15. A static random access memory cell formed on a semiconductor substrate, said memory cell comprising: a first pull-down transistor;   a second pull-down transistor cross-coupled to said first pull-down transistor to form a storage element;   a first polysilicon resistor, coupled to said first pull-down transistor, for pulling-up said first pull-down transistor to a power source;   a second polysilicon resistor, coupled to said second pull-down transistor, for pulling-up said second pull-down transistor to the power source;   a first access transistor coupled to an output port of said first pull-down transistor, so that stored data in the storage element is selectively communicated to a first bitline via said first access transistor, said selective communication through said first access transistor being controlled by a wordline; and   a second access transistor coupled to an output port of said second pull-down transistor, so that stored data in the storage element is selectively communicated to a second bitline via said second access transistor, said selective communication through said second access transistor being controlled by the wordline,   wherein said first polysilicon resistor is placed over a gate of said second pull-down transistor with substantial overlapping therebetween, when the gate of said second pull-down transistor is at a low potential, a depletion region is generated between overlapped said first polysilicon resistor and said second pull-down transistor, obstructing movement of electrons in said first polysilicon resistor, thereby increasing resistance of said first polysilicon resistor and decreasing a standby current of said first polysilicon resistor, and   said second polysilicon resistor is placed over said first pull-down transistor with substantial overlapping therebetween, when the gate of said first pull-down transistor is at a low potential, a depletion region is generated between overlapped said second polysilicon resistor and said first pull-down transistor, obstructing movement of electrons in said second polysilicon resistor thereby increasing resistance of said second polysilicon resistor and decreasing a standby current of said second polysilicon resistor.   
     
     
       16. The memory cell according to claim 15, wherein said first pull-down transistor comprises an NMOS transistor. 
     
     
       17. The memory cell according to claim 15, wherein said second pull-down transistor comprises an NMOS transistor. 
     
     
       18. The memory cell according to claim 15, wherein said first access transistor comprises an NMOS transistor. 
     
     
       19. The memory cell according to claim 15, wherein said second access transistor comprises an NMOS transistor.