Multi-port multiple-simultaneous-access DRAM chip

Abstract

Provides within a semiconductor chip a plurality of internal DRAM arrays connected to each section data bus. A cross-point switch simultaneously connects the plural section data buses to a corresponding plurality of port registers that transfer data between a plurality of ports (I/O pins) on the chip and the section data buses in parallel in either data direction to effectively support a high multi-port data rate to/from the memory chip. For any section, the data may be transferred entirely in parallel between the associated port and a corresponding port register, or the data may be multiplexed between each port and its port register in plural sets of parallel bits. Each of the DRAM banks in the chip is addressed and accessed in parallel with the other DRAM banks through a bank address control in the chip which receives all address requests from four processors in a computer system. Each section data bus is comprised of a large number of data lines that transfer data bits in parallel to/from all of DRAM cells in an address-selected row in one of the DRAM banks at a time in each section. The four DRAM section buses in the chip may be transferring data at the same time in independent directions to/from the four chip ports.

We claim: 
     
       1. A semiconductor memory chip having thereon a large number of DRAM memory cells for use in a computer memory, comprising the following elements being within the chip: a plurality of memory sections, each memory section containing a plurality of DRAM banks,   each DRAM bank containing a plurality of the DRAM cells, each DRAM bank also containing a latch buffer for latching a binary state of a selected row of DRAM cells in the DRAM bank, the latch buffer inputting/outputting data for the selected row,   a plurality of section data buses, each section data bus being connected to the latch buffers of the plurality of DRAM banks of one of the memory sections,   bank address control circuits for receiving memory access request addresses and for selecting one of the DRAM banks containing each requested address, and the DRAM bank selecting the row containing the requested address and setting the latch buffer of the DRAM bank to a bit state of the row while up to all of the other DRAM banks in all of the sections in the chip are simultaneously accessing other requested data, a plurality of input/output ports for transferring data signals between the chip and processors, and a cross-point switch within the chip for simultaneously connecting the section data buses to the input/output ports along selected switched paths, the switched paths independently transferring randomly accessed data between DRAM banks currently selected for accessing requested addresses and input/output ports connected to processors providing the requested addresses,   an input/output selection control connected to the cross-point switch for controlling selections of switched paths in the cross-point switch in response to current requests from processors,   a plurality of port registers respectively associated with the input/output ports, and the port registers connected to one side of the switched paths and the section data buses connected to the other side of the switched paths in the cross-point switch, and   a multiplexor connected between each port and an associated port register to enable a subset of bits in the port register to be transferred in parallel between the port register and the associated port, the subset of bits being a unit of parallel transfer between the chip and a requesting processor, and no multiplexer being required in the chip when all bits in the port register are transferred in parallel between the port register and the associated port.   
     
     
       2. A semiconductor chip having thereon a large number of DRAM memory cells as defined in claim 1, further comprising within the chip: any of the section data buses transferring a plurality of parallel groups of bits of the row in the latch register of one of the DRAM banks currently connected to the section data bus and one of the port registers connected to the same switched path as the section data bus.   
     
     
       3. A semiconductor chip having thereon a large number of DRAM memory cells as defined in claim 2, further comprising within the chip: a clocking input to the chip being provided by processor clocking circuits, switched paths in the cross-point switch being selected and set up prior to a data transfer on the section data buses, and parallel data transfers between the port registers and section data buses being synchronized by the clocking input.   
     
     
       4. A semiconductor chip having thereon a large number of DRAM memory cells as defined in claim 3, further comprising within the chip: data transfers on the plural section data buses being provided in parallel from different DRAM banks in different sections for different processor memory access requests.   
     
     
       5. A semiconductor chip having thereon a large number of DRAM memory cells as defined in claim 4, further comprising within the chip: the data transfers provided in parallel on different section data buses being bidirectionally independent of each other.   
     
     
       6. A semiconductor chip having thereon a large number of DRAM memory cells as defined in claim 5, further comprising within the chip: a switch for connecting the row latch in each DRAM bank to one of the section data buses for an input/output cycle when the DRAM bank has a row latched in its row buffer.   
     
     
       7. A semiconductor chip having thereon a large number of DRAM memory cells as defined in claim 6, further comprising within the chip: the plurality of ports being connected to different processors, and   plural bidirectional data transfer paths in the cross-point switch being set up prior to each data transfer occurring between the DRAM banks and the section data bus, and the data transfer paths connecting the section data buses to the ports connected to processors requesting the data being transferred on the section data buses.   
     
     
       8. A semiconductor chip having thereon a large number of DRAM memory cells as defined in claim 7, further comprising within the chip: each of the data transfers on the plurality of section data buses being made during a predetermined number of processor cycles.   
     
     
       9. A semiconductor chip having thereon a large number of DRAM memory cells as defined in claim 8, further comprising within the chip: one or more processor cycles during simultaneous accesses in a plurality of DRAM banks overlapping one or more processor cycles during simultaneous transfers by a different set of DRAM banks on a plurality of section data buses.   
     
     
       10. A computer system having a plurality of chips providing a main memory of the computer system, each chip internally structured as defined in claim 1, further comprising a plurality of processors having data buses respectively connected in parallel to plural input/output data ports on each chip,   chip selection circuits connected to address signal lines from the processors for receiving each address signalled by any requesting processor for selecting the chip having the address,   the chip receiving the address signalled to the memory selection circuits for selecting a memory bank containing requested data when the address is located in the bank, and   the selected bank in the chip accessing the requested data at the address, and the chip presenting the requested data to the requesting processor through one of the input/output data ports on the chip.   
     
     
       11. A computer system including a main memory and a plurality of processors; a shared cache memory for the plurality of processors being comprised of at least one other chip made as defined in claim 1, further comprising the plurality of processors respectively connected to independent ports on the chip, and the chip signalling the main memory's chip selection circuits for cancelling an access of requested data in main storage when the request obtains requested data from the shared cache.