Circuitry for emulating asynchronous register loading functions

Abstract

Circuitry is provided that allows a register without an asynchronous loading capability to be asynchronously loaded. Logic gates are provided before and after the register. The logic gates are driven by an output signal from a storage circuit such as a latch. When the output signal has one value the logic gates act as non-inverting buffers. When the output signal has another value the logic gates act as inverters. The circuitry allows the normal synchronous operations of the register to be maintained. A hazard coverage circuit can be provided to prevent glitches from appearing at the output during asynchronous operations. The logic gates may be formed from exclusive OR gates implemented in programmable logic on a programmable logic device.

What is claimed is: 
     
       1. Asynchronously loadable register circuitry having a circuit data input and a circuit data output, comprising: a register without asynchronous loading capabilities having a register data input, a register data output, and a register asynchronous control input;   a storage circuit having two storage circuit inputs and a storage circuit output;   a first logic gate having one input coupled to the circuit data input and another input coupled to the storage circuit output and having an output coupled to the register data input; and   a second logic gate having one input coupled to the register data output and another input coupled to the storage circuit output and having an output coupled to the circuit data output, the first and second logic gates acting as non-inverting buffers when the storage circuit output has a first value and acting as inverters when the storage circuit output has a second value.   
     
     
       2. The circuitry defined in claim 1 further comprising an asynchronous data input coupled to one of the storage circuit inputs and an asynchronous load input coupled to the other storage circuit input. 
     
     
       3. The circuitry defined in claim 2 wherein the asynchronous data input is connected to the circuit data input. 
     
     
       4. The circuitry defined in claim 2 wherein the asynchronous load input is coupled to the register asynchronous control input. 
     
     
       5. The circuitry defined in claim 4 wherein the asynchronous load input is coupled to the register asynchronous control input by an inverter. 
     
     
       6. The circuitry defined in claim 4 wherein the asynchronous load input is coupled to the register asynchronous control input by a NOR gate. 
     
     
       7. The circuitry defined in claim 2 wherein the storage circuit comprises a latch having an enable input and a data input, the asynchronous load input being connected to the enable input and the asynchronous data input being connected to the data input. 
     
     
       8. The circuitry defined in claim 1 further comprising an asynchronous clear input coupled to one of the storage circuit inputs and an asynchronous set input coupled to the other storage circuit input. 
     
     
       9. The circuitry defined in claim 8 wherein the asynchronous clear input is coupled to the register asynchronous control input. 
     
     
       10. The circuitry defined in claim 9 wherein the asynchronous clear input is coupled to the register asynchronous control input by a NOR gate. 
     
     
       11. The circuitry defined in claim 8 wherein the asynchronous set input is coupled to the register asynchronous control input. 
     
     
       12. The circuitry defined in claim 11 wherein the asynchronous set input is coupled to the register asynchronous control input by a NOR gate. 
     
     
       13. The circuitry defined in claim 8 wherein the storage circuit comprises a latch having a reset input and a set input, the asynchronous clear input being coupled to the reset input and the asynchronous set input being coupled to the set input. 
     
     
       14. The circuitry defined in claim 13 wherein the asynchronous clear input is directly connected to the reset input of the latch and the asynchronous set input is directly connected to the set input of the latch. 
     
     
       15. The circuitry defined in claim 13 wherein the asynchronous clear input and the asynchronous set input are coupled to the register asynchronous control input by a NOR gate. 
     
     
       16. The circuitry defined in claim 15 further comprising: an asynchronous load input coupled to the register asynchronous control input by the NOR gate; and   an asynchronous data input.   
     
     
       17. The circuitry defined in claim 16 further comprising: a first circuit for coupling the asynchronous clear input and the asynchronous load input to the reset input of the latch; and   a second circuit for coupling the asynchronous set input and the asynchronous data input to the set input of the latch, so that the latch is set and reset by one of: (a) the asynchronous clear input and asynchronous set input and (b) the asynchronous data input and the asynchronous load input.   
     
     
       18. The circuitry defined in claim 1 wherein the register asynchronous control input is a clear input. 
     
     
       19. The circuitry defined in claim 1 further comprising a hazard coverage circuit coupled between the output of the second logic gate and the circuit data output. 
     
     
       20. The circuitry defined in claim 1 wherein the first logic gate is an exclusive OR gate. 
     
     
       21. The circuitry defined in claim 1 wherein the second logic gate is an exclusive OR gate. 
     
     
       22. The circuitry defined in claim 1 further comprising programmable logic in which the first and second gates are implemented. 
     
     
       23. The circuitry defined in claim 1 further comprising: a first look-up table in which the first logic gate is implemented; and   a second look-up table in which the second logic gate is implemented.   
     
     
       24. A digital processing system comprising: a processor;   a memory coupled to the processor; and   a programmable logic device coupled to the processor and the memory, the programmable logic device including asynchronously loadable register circuitry having: a circuit data input,   a circuit data output,   a register without asynchronous loading capabilities having a register data input, a register data output, and a register asynchronous control input,   a storage circuit having two storage circuit inputs and a storage circuit output,   a first logic gate having one input coupled to the circuit data input and another input coupled to the storage circuit output and having an output coupled to the register data input, and   a second logic gate having one input coupled to the register data output and another input coupled to the storage circuit output and having an output coupled to the circuit data output, the first and second logic gates acting as non-inverting buffers when the storage circuit output has a first value and acting as inverters when the storage circuit output has a second value.