Semiconductor memory having bitline precharge circuit

Abstract

A semiconductor device is provided having a symmetric bitline precharge circuit. Sizes of a parasitic devices near transistors lying symmetrically in the bitline precharge circuit are symmetrical to each other. Further, a layout area occupied by the bitline precharge circuit or a chip is reduced or minimized by the symmetric layout. The device can include a memory having first and second bitline extending in parallel a first direction a bitline precharge voltage supplying line and a bitline equalizing signal line extending in parallel in a second direction perpendicular to the first direction. A gate has at least a first part extending in the first direction, a second part having a first predetermined length extending in the second direction coupled to the first part and a third part having a second predetermined length extending in the second direction coupled to the first part with contact areas at uncoupled ends. An active region is on portions of the first and second bitline, the bitline precharge voltage supplying line, the first part and the second part of the gate. A first contact located between the first and second bitline to electrically couples the bitline precharge voltage supplying line and the active region. Second and third contacts electrically couple the gate to the bitline equalizing signal line, and fourth and firth contacts electrically couple the first and the second bitlines to the active region.

What is claimed is: 
     
       1. A semiconductor memory having a bitline precharge circuit, comprising: first and second bitlines extending in parallel along a first direction separated by a prescribed distance;   a bitline precharge voltage line extending in a second direction substantially perpendicular to the first direction;   a gate having a first part extending in the second direction and a second part having a prescribed length extended in the first direction from the first part, wherein both uncoupled ends of the second part have respective first and second contact areas, and wherein the second part is symmetric with reference to one end of the first part;   a bitline equalizing signal line extending in the second direction connecting the first and second contact areas;   an active region on portions of the first and second bitlines, the bitline precharge voltage line, the first part and the second part;   a first contact electrically coupling the bitline precharge voltage line to the active region, wherein the first contact is between said first and second bitline over both said bitline precharge voltage supplying line and said active region;   second and third contacts electrically coupling the gate to said bitline equalizing signal line, wherein the second and third contacts are respectively where the bitline equalizing signal line crosses the first and second contact areas; and   fourth and fifth contacts respectively on said first and second bitlines to electrically couple the said first and second bitlines to said active region.   
     
     
       2. The semiconductor memory having bitline precharge circuit according to claim 1, wherein the third contact is shared with a neighboring bitline precharge circuit when at least two said bitline precharge circuits are neighboring one another in the second direction. 
     
     
       3. The semiconductor memory having bitline precharge circuit according to claim 2, wherein a plurality of transistors among each of the bitline precharge circuits are symmetric so that corresponding parasitic capacitances and resistances are substantially equal in relative separation distances, sizes and locations. 
     
     
       4. The semiconductor memory having bitline precharge circuit according to claim 2, wherein the gate has the same shape relative to each bitline in the bitline precharge circuit. 
     
     
       5. The semiconductor memory having bitline precharge circuit according to claim 1, wherein the gate further comprises a third part extending in the first direction from the first part, wherein the third part is between the bitlines and longer than the second part. 
     
     
       6. The semiconductor memory having bitline precharge circuit according to claim 1, wherein the gate is symmetric relative to a reference point. 
     
     
       7. A semiconductor memory having a bitline precharge circuit and first and second bitline isolation switching devices, comprising: a first bitline extending in a first direction, said first bitline divided into a first and second part of said first bitline;   a second bitline in parallel with said first bitline, said second bitline divided into a first and second part of said second bitline;   a bitline precharge voltage line extending in a second direction substantially perpendicular to the first direction;   a first gate having a first part extending in the second direction and a second part having a prescribed length extended in the first direction from the first part, wherein both uncoupled ends of the second part have respective first and second contact areas, and wherein the second part is symmetric with reference to one end of the first part;   a bitline equalizing signal line extending in the second direction connecting the first and second contact areas;   a second gate having a first part extending in the first direction and a second part having a second prescribed length extended in the second direction from the first part, wherein the uncoupled end of the second part has a third contact area, and wherein the second part is symmetric with reference to one end of the first part of the second gate;   an active region on portions of said second parts of said first and second bitlines, said bitline precharge voltage supplying line and said second part of said gate;   a bitline isolation signal line extending in the second direction, said bitline isolation signal line electrically coupled to said third contact area;   a first contact electrically coupling the bitline precharge voltage line to the active region, wherein the first contact is between said first and second bitline over both said bitline precharge voltage supplying line and said active region;   second and third contacts electrically coupling the gate to said bitline equalizing signal line, wherein the second and third contacts are respectively where the bitline equalizing signal line crosses the first and second contact areas;   fourth and fifth contacts respectively on said first part of the first and second bitlines to electrically couple the first parts of said first and second bitlines to said active region;   sixth and seventh contacts respectively on said second part of the first and second bitlines to electrically couple the said second parts of the first and second bitlines to said active region; and   an eighth contact on the third contact area, wherein the eighth contact electrically couples the second gate to the bitline isolation signal line.   
     
     
       8. The semiconductor memory of claim 7, wherein the third contact is shared with a neighboring bitline precharge circuit when at least two said bitline precharge circuits are neighboring one another in the second direction. 
     
     
       9. The semiconductor memory of claim 8, wherein a plurality of transistors among each of the bitline precharge circuits are symmetric so that corresponding parasitic capacitances and resistances are substantially equal in relative separation distances, sizes and locations. 
     
     
       10. The semiconductor memory of claim 8, wherein the first and second gates have has the same shape relative to each bitline in the bitline precharge circuit. 
     
     
       11. The semiconductor memory of claim 7, wherein the first and second gates are symmetric relative to a reference point. 
     
     
       12. The semiconductor memory of claim 7, wherein said first bitline isolation switching device includes both the fourth contact and the sixth contact, and wherein the second bitline isolation switching device includes both the fifth contact and the seventh contact. 
     
     
       13. A semiconductor memory having a bitline precharge circuit, comprising: first and second bitlines extending in a first direction, said first and second bitlines respectively divided into a first and second parts;   a first line extending in a second direction substantially perpendicular to the first direction;   a first gate having a first part extending in the second direction and a second part having a prescribed length extended in the first direction from the first part, wherein uncoupled ends of the second part have respective first contact areas, and wherein the second part is symmetric with reference to one end of the first part;   a second line extending in the second direction between and electically coupled to the first contact areas;   a second gate having a first part extending in the first direction and a second part having a second prescribed length extended in the second direction from the first part, wherein the uncoupled end of the second part has a second contact area;   an active region;   a third line extending in the second direction, the third line electrically coupled to the second contact area;   a first contact electrically coupling the first line to the active region, wherein the first contact is between said first and second bitline over both the first line and the active region;   second contacts electrically coupling the gate to the second line, wherein the second contacts are respectively where the second line crosses the first contact areas;   third contacts respectively on the first part of the first and second bitlines to electrically couple the first parts of said first and second bitlines to the active region; and   fourth contacts respectively on the second part of the first and second bitlines to electrically couple the second parts of the first and second bitlines to the active region.   
     
     
       14. The semiconductor memory of claim 13, wherein a selected one of the first contact areas is shared with a neighboring bitline precharge circuit when at least two said bitline precharge circuits are neighboring one another in the second direction.