One-time programmable element having controlled programmed state resistance

Abstract

A one-time non-conductive programmable element which is programmable to conduct current is provided. The programmable element comprises several anti-fuses connected in parallel with each other. According to one embodiment of the present invention, each anti-fuse of the programmable element includes first and second conductive plates and a dielectric layer between the two conductive plates. The first conductive plates of all anti-fuses are connected to each other and the second conductive plates of the anti-fuses are connected to each other to form the programmable element of the present invention. The programmable element provides a larger total surface area of the dielectric layer through several anti-fuses that are connected in parallel with each other. During programming, the larger surface area substantially improves the likelihood of capturing a higher defect area of the dielectric layer than was previously possible and allows the formation of strong electrical contact between the two plates having a programmed state resistance that can be controlled with relative accuracy.

I claim: 
     
       1. A one-time non-conductive programmable element formed in an integrated circuit structure and programmable to a controlled programmed state resistance to conduct current therethrough, comprising: a plurality of anti-fuses corresponding in number to the desired programmed state resistance of said programmable element, each anti-fuse including: a first conductive layer;   a second conductive layer; and   a dielectric layer disposed between the first and the second conductive layers, the first conductive layers of the plurality of anti-fuses being connected to each other and the second conductive layer of the plurality of anti-fuses being connected to each other, wherein each anti-fuse is formed by a plurality of generally U-shaped first plates positioned adjacent, and interconnected, to each other, a layer of insulation covering said first plates, and a layer of conductive material covering said insulation to form a plurality of interconnected, generally U-shaped second plates that are surrounded by respective first plates whereby said first and second plates form the plurality of anti-fuses connected in parallel with each other.     
     
     
       2. The one-time programmable element according to claim 1 wherein the number of the plurality of anti-fuses ranges between 4 and 16. 
     
     
       3. The one-time programmable element according to claim 1 wherein the first or second conductive layer is an N+ diffusion layer. 
     
     
       4. The one-time programmable element according to claim 1 wherein the dielectric layer contains an oxide, nitride, nitride-oxide, oxide-nitride-oxide, or undoped amorphous silicon. 
     
     
       5. A one-time non-conductive programmable element formed in an integrated circuit structure and programmable to a controlled programmed state resistance to conduct current therethrough, comprising: a plurality of anti-fuses corresponding in number to the desired programmed state resistance of said programmable element, each anti-fuse including: a first conductive layer;   a second conductive layer; and   a dielectric layer disposed between the first and second conductive layers, the first conductive layers of the plurality of anti-fuses being connected to each other and the second conductive layers of the plurality of anti-fuses being connected to each other, whereby the plurality of anti-fuses are connected in parallel with each other and wherein the first or second conductive layer is an N+ diffusion layer.     
     
     
       6. The one-time programmable element according to claim 5 wherein the dielectric layer contains an oxide, nitride, nitride-oxide, oxide-nitride-oxide, or undoped amorphous silicon. 
     
     
       7. The one-time programmable element according to claim 5 wherein each first conductive layer, the respective second conductive layer and the respective portion of the dielectric material disposed therebetween defines a capacitor. 
     
     
       8. A one-time non-conductive programmable element formed in an integrated circuit structure and programmable to a controlled programmed state resistance to conduct current therethrough, comprising: a plurality of first conductive plates;   a plurality of second conductive plates, each second conductive plate facing a respective first conductive plate, the plurality of first conductive plates connected to each other and the plurality of second conductive plates connected to each other, the number of first and second conductive plates corresponding to the desired programmed state resistance of said programmable element; and   a dielectric material having a plurality of portions with each portion being disposed between each first conductive plate and the respective second conductive plate, and wherein the plurality of first conductive plates is a contiguous conductive layer.   
     
     
       9. An anti-fuse formed in an integrated circuit structure and programmable to a controlled programmed state resistance to conduct current therethrough, comprising: a conductive layer having a plurality of portions;   a plurality of conductive plates, each conductive plate facing a respective one of said plurality of portions of the conductive layer, the plurality of conductive plates being connected to each other, said conductive plates corresponding in number to a desired cumulative probability for the programmed state resistance of said programmable element; and   a dielectric material disposed between each conductive plate and the respective portion of the conductive layer, wherein a portion of the dielectric material breaks down to create a conduction channel when a programming signal is applied between the conductive layer and the plurality of conductive plates.   
     
     
       10. The anti-fuse according to claim 9 wherein the plurality of conductive plates is a contiguous layer. 
     
     
       11. The anti-fuse according to claim 9 wherein the number of the plurality of conductive plates ranges between 4 and 16. 
     
     
       12. An integrated memory device, comprising: a plurality of memory circuits;   an address decoder connected to the plurality of memory circuits and operable to select one memory circuit among the plurality of memory circuits;   a redundant memory select circuit connected to the address decoder and including at least one one-time programmable element, each programmable element including: a plurality of anti-fuses, each anti-fuse including: a first conductive layer;   a second conductive layer; and   a dielectric layer disposed between the first and second conductive layers, wherein the first conductive layers of the plurality of anti-fuses are connected to each other and the second conductive layers of the plurality of anti-fuses are connected to each other, wherein each anti-fuse is formed by a plurality of generally U-shaped first plates positioned adjacent, and interconnected, to each other, a layer of insulation covering said first plates, and a layer of conductive material covering said insulation to form a plurality of interconnected, generally U-shaped second plates that are surrounded by respective first plates whereby the anti-fuses are coupled to each other in parallel; and       a redundant memory circuit connected to the redundant memory select circuit, the redundant memory select circuit being operable to select the redundant memory circuit based on the program state of the programmable element.   
     
     
       13. A method of controlling the programmed state resistance of a one-time programmable element, comprising: selecting a desired cumulative probability for the programmed state resistance of said programmable element;   placing a plurality of anti-fuses in parallel with each other, the number of said anti-fuses corresponding to the selected cumulative probability for the programmed state resistance of said programmable element.