Fast determination of carry inputs from lower order product for radix-8 odd/even multiplier array

Abstract

A multiplier in a floating point processor includes a circuit to determine for each bit of the multiplier operand a 3 times booth recode and a booth recode multiplier array which implements a 3 times booth recode multiplication. The multiplier includes logic to determine a fast sign extend to replace bit positions shifted in the array as well as a rounding adder to provide a rounded result while determining the final result from the booth recode multiplier. The multiplier also includes a circuit to determine a contribution to the final multiplication result from a lower order product with out forming the entire product.

What is claimed is: 
     
       1. An apparatus multiplying a pair of floating point numbers comprising: a booth recode multiplier array responsive to fractional portions of the pair of floating point numbers, said array having a plurality of pipelined rows for determining in each row partial products;   a lower order product array having a row corresponding to each row of the multiplier array, said lower order product array responsive to shifted bits from the multiplier array to determine a contribution to the multiplication result from a lower order product; and   means, responsive to said booth recode multiplier array and said lower order product array, for providing a final product.   
     
     
       2. The apparatus of claim 1 further comprising: means for combining sum and carry vector from said multipler array and bits from said lower order product array corresponding to a contribution to the final product to produce the final product.   
     
     
       3. The apparatus of claim 1 wherein the lower order product array comprises: a half adder fed by shifted corresponding product bits from a multiplier array, said half adder producing carry and sum bits;   means, responsive to the carry and sum bits from the half adder, for producing a sum and a carry vector for the corresponding row of the multiplier array; and   means, responsive to a carry out for a one of said rows preceding a last one of said rows, for combining a last one of the sum and carry vectors corresponding to a last one of the rows of the multiplier array to provide the contribution to the multiplication product from the lower order product.   
     
     
       4. The apparatus of claim 1 wherein said multiplier array produces partial products without considering contributions from the lower order product array.