Electronic computer memory system having multiple width, high speed communication buffer

Abstract

An electronic computer memory system has first and second intermediate memory levels for use between a central processing unit and a main memory level. One or more buffer arrays have two sets of bus lines. A first set of buffer array bus lines communicates with associated bus lines of the first and second intermediate memory arrays. The second set of buffer array bus lines contains a number of bus lines less than the number of bus lines in the first memory array. By providing one or more buffers with two sets of bus lines, data can be transferred between the main memory level and the buffer or one intermediate memory level while data in the other intermediate memory level is operated on by a the central processing unit. By providing the buffer with one set of bus lines equal to the number of bus lines of the first and second intermediate memory arrays, high speed data transfer between the intermediate memory arrays can be achieved.

We claim: 
     
       1. An electronic computer memory system, comprising: a first multidimensional memory array having a first port and a second port;   a second multidimensional memory array having a first port;   a main memory array;   a first bidirectional data transfer path connecting the main memory array and the first port of the first memory array, the first bidirectional data transfer path bypassing the second memory array;   a second bidirectional data transfer path connecting the main memory array and the first port of the second memory array, the second bidirectional data transfer path bypassing the first memory array;   a third bidirectional data transfer path connecting the second port of the first memory array and a processing unit;   a wide, high speed bidirectional data path connecting the first port of the first memory array and the first port of the second memory array;   means for facilitating bidirectional data transfer between the main memory array and the second memory array simultaneously with data transfer between the first memory array and the processing unit;   wherein the first and second memory arrays and the wide, high speed data path reside in a single, monolithic integrated circuit chip.   
     
     
       2. The memory system of claim 1, wherein the first memory array includes a first decoder associated with the first port and a second decoder associated with the second port, the first decoder and second decoder allowing independent data writes and reads to and from the first and second ports of the first memory array. 
     
     
       3. The memory of claim 2, wherein: the first memory array includes a plurality of rows of a first number of memory cells and a first access speed; and   the second memory array includes rows of a second plurality of memory cells and a second access speed slower than the first access speed.   
     
     
       4. The memory system of claim 2 wherein the wide, high speed data path connecting the first port of the first memory level and the first port of the second memory level comprises a first buffer array having an input/output port coupled to the first ports of the first and second memory arrays. 
     
     
       5. The memory system of claim 3, wherein the wide, high speed data path connecting the first port of the first memory level and the first port of the second memory level comprises a first buffer array having an input/output port coupled to the first ports of the first and second memory arrays. 
     
     
       6. The memory system of claim 5, wherein the second memory array further comprises an error correcting circuit connected to receive data from memory cells of the second memory array. 
     
     
       7. The memory system of claim 4, wherein the wide, high speed data path further comprises a second buffer array, having an input/output port coupled to the first ports of the first and second memory arrays. 
     
     
       8. The memory system of claim 7, wherein the first buffer array and the second buffer array each comprise a second port for receiving and transferring data to and from the main memory array, the first and second buffers thereby constituting independent branches of the first bidirectional data transfer path. 
     
     
       9. The memory system of claim 7, wherein the first memory array is a static random access memory. 
     
     
       10. The memory system of claim 7, wherein the second memory array is a dynamic random access memory. 
     
     
       11. The memory system of claim 7, wherein the input/output ports of the first and second buffer arrays each comprise a number of bus lines equal to the first number of memory cells. 
     
     
       12. The memory system of claim 11, wherein the second ports of the first and second buffer arrays each comprise a number of bus lines less than the first number of memory cells. 
     
     
       13. A system, comprising: (a) a main memory having a number of cells;   (b) a single integrated circuit chip, comprising: (i) a first multidimensional memory array having fewer cells than the main memory;   (ii) a second multidimensional memory array having more cells than the first memory array and a slower access speed and fewer cells than the main memory;   (iii) the first memory array having a first port for communicating with an off-chip processor and a second port for communicating with the second memory array via a wide, high speed, on-chip data path;   (iv) means for transferring data between the first memory array and the main memory while bypassing the second memory array, and between the second memory array and the main memory while bypassing the first memory array.     
     
     
       14. The system of claim 13, wherein the first memory array is an SRAM and the second memory array is a DRAM. 
     
     
       15. The system of claim 14, wherein the first memory array comprises a plurality of rows of a number, n, of memory cells, and wherein the wide, high-speed, on-chip data path comprises n lines. 
     
     
       16. The system of claim 15, wherein the wide, high speed, on-chip data path further comprises an on-chip first buffer array having a port with n data lines, the buffer array port being coupled to receive/transmit data from/to the first and second memory arrays.