Semiconductor memory device equipped with an equalizing control circuit having a function of latching an equalizing signal

Abstract

The present invention relates to a semiconductor memory device which, while preventing an operation error, achieves the shortening of a precharging time and, hence, further shortening of a cycle time of a memory operation. The equalizing control circuit includes a latch circuit. An equalizing control circuit receives a signal WLact and a signal X-ADR from a predecoder and outputs an equalizing signal EQS from these two signals. A latch circuit in the equalizing control circuit is set (the inactivation of an equalizing signal) by a signal X-ADR which is activated with an internal RAS signal and holds its state. The latch circuit is reset (the activation of the equalizing signal) by a signal corresponding to a word line active signal WLact with a word line inactivated. By doing so, it is possible to provide the equalizing control circuit not directly depending upon the internal RAS signal.

I claim: 
     
       1. A semiconductor memory device comprising: a memory cell array activated to select at least one memory cell, said memory cell array comprising dynamic memory cells requiring a restoring operation;   a plurality of bit lines connected to said dynamic memory cells for allowing a data signal to be transferred into and out of said memory cell array;   an equalizing circuit, responsive to an equalizing signal prior to activating said memory cell array, for balancing a potential level on said bit lines; and   an equalizing signal control circuit including a latch circuit for controlling the equalizing signal, the equalizing signal being set to an activating level responsive to an inactivation level of a word line active signal for controlling decode timing of word lines and to a non-activating level responsive to a signal corresponding to an inputting of an address signal for selecting said memory cell.   
     
     
       2. A semiconductor memory device comprising: a memory cell array having a plurality of memory cells arranged in a row and column matrix array;   a plurality of word lines connected to control nodes of the memory cells in corresponding rows of said memory cell array, said word lines being activated upon being supplied with predetermined voltage,   a plurality of bit lines connected to transfer nodes of the memory cells in corresponding columns of said memory cell array to allow a data signal to be transferred into and out of the memory cell array;   equalizing transistors electrically connected between a predetermined number of said bit lines and a predetermined potential node, said equalizing transistors equalizing potential levels on said bit lines prior to the activation of said word lines; and   an equalizing signal control circuit, equipped with a latch circuit, for controlling an equalizing signal supplied to gates of said equalizing transistors, the equalizing signal being set to an activation level responsive to an inactivation level of a word line active signal for controlling decode timing of said word lines and to a non-activation level responsive to the inputting of an address signal for selecting one of said memory cells.   
     
     
       3. The semiconductor memory device according to claim 2, wherein the equalizing signal control circuit includes a level shift circuit. 
     
     
       4. A semiconductor memory device comprising: a memory cell array having a plurality of memory cells arranged in a row/column matrix;   a plurality of word lines connected to control nodes of the memory cells in corresponding rows of said memory cell array;   a plurality of bit lines connected to transfer nodes of the memory cells in corresponding columns of said memory cell array to allow a data signal to be transferred into and out of said memory cell array;   equalizing transistors electrically connected between a predetermined number of said bit lines and predetermined potential node, said equalizing transistors equalizing potentials of said bit lines when said memory cell array is inactivated; and   an equalizing signal control circuit for allowing an equalizing signal which is applied to gates of said equalizing transistors to be in an activated state in accordance with an inactivation level of a word line active signal for controlling decode timing of said word lines and to be in a non-activated state in accordance with an address signal corresponding to an external signal which is directed to said memory cell array.   
     
     
       5. The semiconductor memory device according to claim 4, wherein the equalizing signal control circuit includes a level shift circuit. 
     
     
       6. The semiconductor memory device according to claim 2 or 4, wherein the memory cell array is divided into blocks and only a predetermined memory cell array block is activated in accordance with the address signal. 
     
     
       7. A semiconductor memory device comprising: a plurality of memory cell arrays each having a plurality of memory cells in a row/column matrix array, said memory cell arrays comprising dynamic memory cells requiring a restoring operation;   a plurality of word lines connected to control nodes of the memory cells in corresponding rows of said memory cell arrays and being activated upon being supplied with a predetermined voltage;   a plurality of bit lines connected to transfer nodes of the memory cells in corresponding columns of said memory cell arrays to allow a data signal to be transferred into and out of said memory cell array;   equalizing transistors electrically connected between a predetermined number of said bit lines and a predetermined potential node; and   equalizing signal control circuits each provided for a corresponding one of said memory cell arrays, and equipped with a flip-flop for allowing an equalizing signal which is applied to gates of said equalizing transistors to be in an activated state in accordance with an inactivation level of a word line active signal for controlling decode timing of said word lines and to be made to a non-activated state in accordance with an address signal corresponding to an external signal which is directed to one of said memory cell arrays.   
     
     
       8. The semiconductor memory device according to claim 7, wherein the equalizing signal control circuit includes a level shift circuit. 
     
     
       9. The semiconductor memory device according to claim 7 or 8, wherein the memory cell array is divided into blocks and only a predetermined memory cell array block is activated in accordance with the address signal. 
     
     
       10. A semiconductor memory device including a flip-flop circuit for controlling equalizing circuitry for, prior to activating a memory cell array, balancing potential levels on a plurality of bit lines for transferring a signal into and out of said memory cell array in which said flip-flop circuit allows said equalizing circuitry to be activated in accordance with an inactivation level of a word line active signal for controlling decode timing of word lines and to be non-activated in accordance with an address signal corresponding to an external signal which is directed to said memory cell array. 
     
     
       11. A semiconductor memory device comprising: a memory cell array comprising memory cells arranged in rows and columns;   bit lines coupled to the memory cells in the columns of said memory cell array;   word lines coupled to the memory cells in the rows of said memory cell array;   equalizing circuitry for equaling potentials of said bit lines; and   equalizing control circuitry for generating an equalizing signal supplied to said equalizing circuitry, said equalizing control circuitry comprising a latch circuit which is set to generate a signal for deactivating said equalizing circuitry based on a first signal generated in response to an address signal for selecting said memory cells, and which is reset to generate a signal for activating said equalizing circuit based on a second signal generated in response to an inactivation level of a word line active signal for controlling decode timing of said word lines.   
     
     
       12. The semiconductor memory device according to claim 11, wherein said latch circuit comprises a flip-flop. 
     
     
       13. The semiconductor memory device according to claim 11, wherein said equalizing control circuitry further comprises a level-shift circuit. 
     
     
       14. The semiconductor memory device according to claim 11, wherein said equalizing circuitry comprises equalizing transistors connected between said bit lines and a potential node, the equalizing control signal being supplied to control terminals of said equalizing transistors. 
     
     
       15. The semiconductor memory device according to claim 11, wherein said memory cells comprise dynamic memory cells. 
     
     
       16. A semiconductor memory device comprising: a plurality of memory cell arrays activated to select at least one memory cell, said memory cell arrays comprising dynamic memory cells requiring a restoring operation;   a plurality of bit lines connected to said dynamic memory cells for allowing a data signal to be transferred into and out of said memory cell arrays;   equalizing circuits, responsive to an equalizing signal prior to activating said memory cell arrays for balancing a potential level on said bit lines; and   equalizing signal control circuits each provided for a corresponding one of said memory cell arrays, and including a latch circuit for controlling the equalizing signal, the equalizing signal being set to an activating level responsive to an inactivation level of a word line active signal for controlling decode timing of word lines and to a non-activating level responsive to a signal corresponding to an inputting of an address signal for selecting said memory cell.