Digital counter and digital phase locked loop circuit using same

Abstract

A digital counter comprised of a synchronization judgement circuit and a counting circuit, the synchronization judging circuit receiving as an input signal the results of a comparison from a phase comparison circuit which compares the phase of a reference signal and an output signal of a frequency factoring circuit and outputting a phase synchronization judgement signal to the counting circuit, the counting circuit receiving as input the results of comparison and the phase synchronization judgement signal, performing a count based on the results of comparison, and successively determining a count from the most significant bit to the least significant bit. Also, a digital PLL circuit using the digital counter.

What is claimed is: 
     
       1. A digital counter comprising: a synchronization judging means; and   a counting means; wherein: said synchronization judging means receives as an input signal results of a comparison from a phase comparison circuit which compares a phase of a reference signal and a phase of an output signal of a frequency factoring means;   said synchronization judging means outputs a phase synchronization judgment signal to said counting means;   said counting means receives as input said results of said comparison and said phase synchronization judgment signal and performs a count based on said results of the comparison, successively determining said count from a most significant bit to a least significant bit; and   said counting means successively determines the count from the most significant bit to the least significant bit based on said results of said comparison until said phase of said output signal of said frequency factoring means is synchronized with said phase of said reference signal, and said counting means changes the count from the least significant bit to the most significant bit based on the results of the comparison after synchronization of the phase of said reference signal and said output signal of said frequency factoring means.     
     
     
       2. A digital counter as set forth in claim 1, wherein: said counting means has a first counting means and a second counting means;   said first counting means successively determines the count from the most significant bit to the least significant bit based on said results of said comparison until said phase of said output signal of said frequency factoring means is synchronized with said phase of said reference signal; and   said second counting means changes the count from the least significant bit based on the results of the comparison after synchronization of the phase of said reference signal and said output signal of said frequency factoring means.   
     
     
       3. A digital phase locked loop (PLL) circuit comprising: a frequency factoring means;   a phase comparing means for comparing a phase of a reference signal and a phase of an output signal of said frequency factoring means; and   a digital counter having a counting means and a synchronization judging means;   wherein said synchronization judging means receives as input results of the comparison from said phase comparing means and outputs to said counting means a phase synchronization judgment signal, and   wherein said counting means successively determines a count from a most significant bit to a least significant bit based on said results of said comparison and outputs said count to said frequency factoring means; and   further wherein the count is changed from the least significant bit to the most significant bit based on the results of said comparison after the phases of the reference signal and the output signal of the frequency factoring means are synchronized.   
     
     
       4. A digital PLL circuit as set forth in claim 3, wherein said frequency factoring means comprises a frequency multiplying means and a frequency dividing means connected in cascade. 
     
     
       5. A digital PLL circuit as set forth in claim 3, wherein a position of the most significant bit of said counting means is determined based on a period of said reference signal and a factor of said frequency factoring means. 
     
     
       6. A digital counter comprising: a synchronization judging circuit; and   a counter; wherein: said synchronization judging circuit receives as an input signal results of a comparison from a phase comparison circuit which compares a phase of a reference signal and a phase of an output signal of a frequency factoring circuit;   said synchronization judging circuit outputs a phase synchronization judgment signal to said counter;   said counter receives as input said results of said comparison and said phase synchronization judgment signal and successively determines a count from a most significant bit to a least significant bit; and   said counter successively determines the count from the most significant bit to the least significant bit based on said results of said comparison until said phase of said output signal of said frequency factoring circuit is synchronized with said phase of said reference signal, and changes the count from the least significant bit to the most significant bit based on the results of the comparison after synchronization of the phase of said reference signal and said output signal of said frequency factoring circuit.     
     
     
       7. A digital counter as set forth in claim 6, wherein: said counter has a first counting circuit and a second counting circuit;   said first counting circuit successively determines the count from the most significant bit to the least significant bit based on said results of said comparison until said phase of said output signal of said frequency factoring circuit is synchronized with said phase of said references signal; and   said second counting circuit changes the count from the least significant bit to the most significant bit based on the results of the comparison after synchronization of the phase of said reference signal and said output signal of said frequency factoring circuit.   
     
     
       8. A digital phase locked loop (PLL) circuit comprising: a frequency factoring circuit;   a phase comparing circuit for comparing a phase of a reference signal and a phase of an output signal of said frequency factoring circuit; and   a digital counter having a counting circuit and a synchronization judging circuit;   wherein said synchronization judging circuit receives as input results of the comparison from said phase comparing circuit and outputs to said counting circuit a phase synchronization judgment signal,   wherein said counting circuit successively determines a count from a most significant bit to a least significant bit based on said results of said comparison and outputs said count to said frequency factoring circuit, and   wherein the count is changed from the least significant bit to the most significant bit based on the results of said comparison after the phases of the reference signal and the output signal of the frequency factoring circuit are synchronized.   
     
     
       9. A digital PLL circuit as set forth in claim 8, wherein said frequency factoring circuit comprises a frequency multiplying circuit and a frequency dividing circuit connected in cascade. 
     
     
       10. A digital PLL circuit as set forth in claim 8, wherein a position of the most significant bit of said counting circuit is determined based on a period of said reference signal and a factor of said frequency factoring circuit. 
     
     
       11. A digital phase locked loop (PLL) circuit comprising: a frequency factoring circuit;   a phase comparator which compares a phase of a reference signal and a phase of an output signal of said frequency factoring circuit; and   a digital counter which receives the output of the phase comparator and which successively determines a count from a most significant bit to a least significant bit based on said output of said comparator, said digital counter outputting said count to said frequency factoring circuit;   wherein the count is changed from the least significant bit to the most significant bit based on the results of said comparison after the phases of the reference signal and the output signal of the frequency factoring circuit are synchronized.   
     
     
       12. A digital PLL circuit as set forth in claim 11, wherein said frequency factoring circuit comprises a frequency multiplying circuit and a frequency dividing circuit connected in cascade. 
     
     
       13. A digital phase locked loop (PLL) circuit comprising: a frequency factoring circuit;   a phase comparator for comparing a phase of a reference signal and a phase of an output signal of said frequency factoring circuit;   a synchronization judging circuit; and   a counter;   wherein said synchronization judging circuit receives as input results of the comparison from said phase comparator and outputs to said counter a phase synchronization judgment signal, and   wherein said counter successively determines a count from a most significant bit to a least significant bit based on said results of said comparison and outputs said count to said frequency factoring means,   wherein a position of the most significant bit of said counter is determined based on a period of said reference signal and a factor of said frequency factoring circuit.