Memory access mechanism for a parallel processing computer system with distributed shared memory

Abstract

To increase the capacity of usable memory of a parallel processing computer system as a whole and effectively utilize the address space without waste, a variable-length Global/Local allocation field is provided in a fixed-length address. When the field is locally set, the address is used as an address of a local memory area to which the local processor refers. When the allocation is globally set, the remaining address is a variable length logical processor number (this number is converted into a physical processor number) and a variable length offset address, for specifying a global memory area belonging to a processor out of the global areas of memories of a group of some of the processors, which global memory can be referred to by all the processors of the groups. A memory access interface executes memory access to the local or global area of the memory of the local processor or to the global area of the memory of another processor.

We claim: 
     
       1. A memory access mechanism for a parallel processing distributed/shared memory computer system of a plurality of processors, each having memory, comprising: a fixed length memory access request address having a variable-length Global/Local allocation field, so that when the field is locally set a remainder of the address is a local memory area address, and so that when the Global/Local allocation field is set globally the remainder of the address is a variable-length processor number field for specifying one of processors and a variable length offset field for specifying a Global address on a memory of a processor specified by the processor number field; and   a memory access interface for each of the processors, the memory access interface having means for identifying content of the Global/Local allocation field, means for extracting content of the processor number field, means for extracting content of the offset field, means for starting access to a local memory area when the means for identifying indicates locally set and when the means for identifying indicates set globally and the content of the processor number field indicates a local processor, and means for starting access to memory of another processor other than the local processor by an address of the offset field when the means for identifying indicates set globally and the processor number field indicates the another processor.   
     
     
       2. A memory access mechanism according to claim 1, wherein said means for identifying comprises a mask register for drawing out a part of the memory access request address by use of a mask; said means for extracting content of the processor number field comprises a register for showing bit width of the offset field;   said means for extracting content of the offset field comprises a mask register for drawing out a part of the memory access request address by use of a mask; and   wherein content of each of said mask registers and the content of the register for showing bit width of the offset field, each being rewrittable in accordance with an instruction issued by one of the processors.   
     
     
       3. A memory access mechanism according to claim 1, wherein content of said processor number field is a logical processor number; further including means for converting a logical processor number of said processor number field into a physical processor number; and   wherein each of said means for starting uses said physical processor number.   
     
     
       4. A memory access mechanism according to claim 3, wherein said means for identifying comprises a mask register for drawing out a part of the memory access request address by use of a mask; said means for extracting content of the processor number field comprises a register for showing bit width of the offset field;   said means for extracting content of the offset field comprises a mask register for drawing out a part of the memory access request address by use of a mask; and   wherein content of each of said mask registers and the content of the register for showing bit width of the offset field, each being rewrittable in accordance with an instruction issued by one of the processors.   
     
     
       5. A memory access mechanism according to claim 2, wherein said means for starting access to a local memory area comprises a base address register for holding address addition information for converting an offset head address of said memory access request address to a head address of the local memory area, and the content of said base address register being rewrittable in accordance with an instruction by a processor. 
     
     
       6. A parallel processing computer system, with distributed/shared memory, comprising: a plurality of arithmetic processors;   a plurality of local memories, each locally coupled to a respective one of said processors and being divided into a local memory area and a global memory area;   a network interconnecting the processors for parallel processing as a parallel processing computer system;   each of the processors accessing the local memory area in the locally coupled local memory and the global memory area in each of the local memories of all others of said processors, to provide the parallel processing computer system with distributed/shared memory; and   each of said processors including a memory access interface receiving, storing and processing a fixed bit length memory access address having a variable length processor number field and a variable length memory address field.   
     
     
       7. A parallel processing computer system according to claim 6, further including a processor number converting unit for converting a logical processor number in the variable length processor number field into a physical processor number. 
     
     
       8. A parallel processing computer system according to claim 7, wherein said processor number converting unit includes a conversion table having physical processor number entries and rewrittable logical processor number entries. 
     
     
       9. A parallel processing computer system according to claim 7, further including means for logically defining an arbitrary global group of only some of said processors, means for setting a bit length of the processor number field to a minimum bit length sufficient to logically identify the some of said processors of said global group, and means for setting the memory address field to an offset address of a maximum bit length that uses available bits not used by the setting of the processor number field. 
     
     
       10. A parallel processing computer system according to claim 9, wherein said some of said processors have a memory map with addressable memory size corresponding to the fixed bit length of said memory access address; and wherein said memory access interface of each processor dynamically allocates the global memory area within a locally coupled local memory so that maximum global memory area corresponds in size to maximum memory area that may be addressed according to the maximum bit length of the offset address.   
     
     
       11. A parallel processing computer system according to claim 9, wherein said memory access address includes a global/local identification field, for holding a one bit length value identifying the memory address field as holding a local or a global address; wherein each local memory includes one-half allocation to said local memory area addressable by one value of the global/local identification field, and an other half allocation being said global memory area addressable by another value of said global/local allocation field; and said global memory area being equally divided into memory global allocations, with a number of divisions being equal to a number of processors within the global group and the memory global allocations being respectively addressed by a value in the processor number field, whereby the maximum size of each memory global allocation is dynamically set to a maximum size depending upon the number of dynamically set processors within the global group.     
     
     
       12. A parallel processing computer system according to claim 11, wherein said local memory area is divided between an input/output allocation and a maximum local memory allocation, whereby the local processor globally addresses a divided allocation of the global memory area allocated to the local and other processors of the global group, and locally addresses local memory area of the local memory allocation and the input/output allocation. 
     
     
       13. A parallel processing computer system according to claim 6, further including means for logically defining an arbitrary global group of only some of said processors, means for setting a bit length of the processor number field to a minimum bit length sufficient to logically identify the some of said processors of said global group, and means for setting the memory address field to an offset address of a maximum bit length that uses available bits not used by the setting of the processor number field. 
     
     
       14. A parallel processing computer system according to claim 13, wherein said some of said processors have a memory map with addressable memory size corresponding to the fixed bit length of said memory access address; and wherein said memory access interface of each processor dynamically allocates the global memory area within the locally coupled local memory so that maximum global memory area corresponds in size to maximum memory area that may be addressed according to the maximum bit length of the offset address.   
     
     
       15. A parallel processing computer system according to claim 14, wherein each memory map includes global memory areas for only the some of said processors of said global group and not for others of said processors. 
     
     
       16. A parallel processing computer system according to claim 6, wherein said memory access address includes a global/local identification field, for holding a value identifying the memory address field as holding a local or a global address. 
     
     
       17. A parallel processing computer system according to claim 16, wherein said memory access interface detects whether said global/local identification field identifies local accessing or global accessing, and in response to detecting local accessing interprets all remaining bits of said memory access address, other than the global/local identification field, as a local address in the local memory area, and in response to detecting global accessing interprets the remaining bits as a logical processor number and an address offset within the global memory area of the processor identified by the logical processor number. 
     
     
       18. A parallel processing computer system according to claim 16, wherein the memory access interface includes an other memory access unit runnable only when the global/local identification field indicates a global address, and a separate local memory access unit runnable when the address does not have a global/local identification field indicating global access. 
     
     
       19. A parallel processing computer system according to claim 18, wherein said local memory access unit includes an offset address register for receiving an offset address from said memory address field, a software resettable base address register, an addition unit for adding output of the offset address register and output of the base address register to produce a result, and a result register for holding the result; and said memory access interface further including an input/output access unit for receiving the result from said result register, and sending the result to said local memory area.   
     
     
       20. A parallel processing computer system according to claim 16, including means for software setting said global/local identification field to a variable length, including both a zero bit length and a one bit length. 
     
     
       21. A parallel processing computer system according to claim 20, wherein said memory access interface interprets the value of said global/local identification field, and in response to a zero bit length of said global/local identification field interprets all bits of said memory access address as a local address in the local memory area, and in response to determining a global accessing from said global/local identification field, interprets remaining bits as a logical processor number and an address offset within the global memory area of the processor identified by the logical processor number. 
     
     
       22. A parallel processing computer system according to claim 20, further including means for logically defining an arbitrary global group of only some of said processors, means for setting a bit length of the processor number field to a minimum bit length sufficient to logically identify the some of said processors of said global group, and means for setting the memory address field to an offset address of a maximum bit length that uses available bits not used by the setting of the processor number field. 
     
     
       23. A parallel processing computer system according to claim 22, wherein at least some of said processors have a memory map with addressable memory size corresponding to the fixed bit length of said memory access address; and wherein said memory access interface of each processor dynamically allocates the global memory area within locally coupled local memory so that maximum global memory area corresponds in size to maximum memory area that may be addressed according to the maximum bit length of the offset address.   
     
     
       24. A parallel processing computer system according to claim 6, wherein said processor number field is a physical processor number field. 
     
     
       25. A parallel processing computer system according to claim 6, wherein said memory access interface includes a rewrittable base address register holding address addition information to convert a head offset address from said address field into a physical head address of the local memory area. 
     
     
       26. A parallel processing computer system according to claim 6, wherein each of said processors includes a processor internal bus, an instruction processor, the memory access interface coupled between said instruction processor and said processor internal bus, an input/output device, an input/output interface coupled between said input/output device and said processor internal bus, a memory control coupled between said locally coupled local memory and said processor internal bus, and a network interface coupled between said processor internal bus and said network. 
     
     
       27. A parallel processing computer system according to claim 26, wherein said memory access interface further includes a data register coupled to said processor internal bus for receiving any data from completion of the memory access and sending the data to the said instruction processor, and a completion signal register coupled to said processor internal bus and said instruction processor for sending a completion signal to said instruction processor at the completion of memory access. 
     
     
       28. A parallel processing computer system according to claim 26, wherein said memory access interface further includes a software settable register to separate a processor number from said memory access address, and said memory access interface further including a software settable address mask register for providing a mask to separate an offset address from said memory access address.