Semiconductor integrated circuit device

Abstract

A semiconductor integrated circuit device comprising a one-chip microcomputer having a nonvolatile memory circuit to and from which write and read operations are carried out at high speed in keeping with the cycle time of the processor. Part of the memory circuit is set aside as a read-only area for accommodating a data processing program, and the rest of the memory is used to write and read data thereto and therefrom. With no need to optimize the assignments of the ROM and RAM parts in the memory circuit, the one-chip microchip is easy to design and manufacture with high productivity. With the program storage area established as desired, users enjoy more convenience use of the one-chip microcomputer than before.

What is claimed is: 
     
       1. A semiconductor integrated circuit device formed in a single chip, comprising: a processor for performing predetermined processing according to a program;   a nonvolatile memory circuit having a plurality of memory cells each of which includes a ferroelectric capacitor to be used for storing data; and   a designation circuit which designates a part of the nonvolatile memory circuit as a first area to be allocated to a nonvolatile memory in which a change in stored data in each of the memory cells is prevented, and a different part of the nonvolatile memory circuit to be allocated to a volatile memory in which a chance in stored data in each of the memory cells is permitted.   
     
     
       2. The semiconductor integrated circuit device according to claim 1, wherein said first area stores at least a part of the program. 
     
     
       3. The semiconductor integrated circuit device according to claim 2, wherein said designation circuit includes a register storing address data for indicating the first area and a comparator comparing the stored address data with address data outputted from the processor, and wherein the address data is set to the register by performing predetermined processing according to a program. 
     
     
       4. The semiconductor integrated circuit device according to claim 3, wherein said designation circuit further includes a logic circuit which inhibits the writing of data into the first area in response to an output from the comparator. 
     
     
       5. The semiconductor integrated circuit device according to claim 4, wherein said logic circuit includes a gate which receives the output from the comparator and a write control signal from the processor, the logic control circuit outputting a memory write control signal to the nonvolatile memory. 
     
     
       6. The semiconductor integrated circuit device according to claim 5, wherein each of the memory cells within the second area operates as a dynamic memory cell. 
     
     
       7. The semiconductor integrated circuit device according to claim 6, wherein each of memory cells within the first area operates as a read-only memory cell. 
     
     
       8. The semiconductor integrated circuit device according to claim 6, wherein reading from each of the memory cells within the first area is performed without changing a polarity direction of the ferroelectric capacitor in each of the memory cells. 
     
     
       9. The semiconductor integrated circuit device according to claim 2, wherein the reading from each of the memory cells within the first area is performed without changing a polarity direction of the ferroelectric capacitor in each of the memory cells. 
     
     
       10. A system comprising: a processor for performing at least one predetermined processing operation in accordance with a program;   a nonvolatile memory circuit having a plurality of memory cells each of which includes a ferroelectric capacitor to be used for storing data; and   a designation circuit which designates a part of the nonvolatile memory circuit as a first area to be allocated to a nonvolatile memory in which a change in stored data in each of the memory cells is prevented, wherein a different part of the nonvolatile memory circuit is allocated to a volatile memory in which a change in stored data in each of the memory cells is permitted.   
     
     
       11. The system according to claim 10, wherein said first area stores at least a part of the program. 
     
     
       12. The system according to claim 11, wherein said designation circuit includes a register storing address data for indicating the first area and a comparator comparing the stored address data with address data outputted from the processor, and wherein the address data is set to the register by performing predetermined processing according to a program. 
     
     
       13. The system according to claim 12, wherein said designation circuit further includes a logic circuit which inhibits the writing of data into the first area in response to an output from the comparator. 
     
     
       14. The system according to claim 13, wherein said logic circuit includes a gate which receives the output from the comparator and a write control signal from the processor, the logic control circuit outputting a memory write control signal to the nonvolatile memory. 
     
     
       15. The system according to claim 14, wherein each of the memory cells within the second area operates as a dynamic memory cell. 
     
     
       16. The system according to claim 15, wherein each of the memory cells within the first area operates as a read-only memory cell. 
     
     
       17. The system according to claim 15, wherein reading from each of the memory cells within the first area is performed without changing a polarity direction of the ferroelectric capacitor in each of the memory cells. 
     
     
       18. The system according to claim 11, wherein the reading from each of the memory cells within the first area is performed without changing a polarity direction of the ferroelectric capacitor in each of the memory cells. 
     
     
       19. A semiconductor integrated circuit device formed in a single chip, the semiconductor integrated circuit device comprising: a processor for performing processing operations under control of a program;   a nonvolatile memory circuit having a plurality of memory cells; and   a designation circuit designating a first part of the nonvolatile memory circuit as a first area to be allocated to a nonvolatile memory in which a change of stored data in each of memory cells is inhibited and a different part of the nonvolatile memory circuit is used as a second area to be allocated a volatile memory in which a write operation to change stored data in a memory cell is permitted, the write operation to the second area being performed at a speed corresponding to a cycle time of the processor.   
     
     
       20. The semiconductor integrated circuit device according to claim 19, wherein said designation circuit includes a memory for storing address information representing said first part of said nonvolatile memory, and comparison means for comparing address information output by said processor with the address information stored in said memory, and wherein the address information is set by performing a program on the processor. 
     
     
       21. The semiconductor integrated circuit device according to claim 20, wherein each of said memory cells comprises a ferroelectric capacitor such that a nonvolatile storage operation is performed to each memory cell depending on the direction of the polarity of said ferroelectric capacitor. 
     
     
       22. A semiconductor integrated circuit device formed in a single semiconductor chip, this device comprising: a processor for performing predetermined processing operations according to a program;   a first nonvolatile memory circuit in which a part of said program is stored;   a second nonvolatile memory circuit having a plurality of memory cells; and   a designation circuit designating a first part of the second nonvolatile memory circuit as a first area to be allocated to a nonvolatile memory in which a different part of the program is stored and in which a change of stored data in each of memory cells is inhibited, and a part of the second nonvolatile memory circuit as a second area to be allocated a volatile memory in which a write operation to change stored data in a memory cell is permitted, the write operation in the second area being performed at a speed corresponding to a cycle time of the processor.   
     
     
       23. The semiconductor integrated circuit device according to claim 22, wherein said designation circuit includes, a memory for storing address information representing said first part of said second nonvolatile memory, and   a comparison means for comparing address information output by said processor with the address information stored in said memory, the address information being set by performing the program with the processor.   
     
     
       24. The semiconductor integrated circuit device according to claim 23, wherein each of said memory cells has a ferroelectric capacitor such that a nonvolatile storage operation is performed to the memory cell in accordance with the direction of the polarity of said ferroelectric capacitor. 
     
     
       25. A system comprising: a processor for performing predetermined processing according to a program;   a nonvolatile memory circuit having a plurality of memory cells; and   a designation circuit designating a first part of the nonvolatile memory circuit as a first area to be allocated to a nonvolatile memory in which a change of stored data in each of memory cells is inhibited and a different second part of the nonvolatile memory circuit is used as a second area to be allocated a volatile memory in which a write operation to change stored data in a memory cell is permitted, the write operation to the second area being performed at a speed in keeping with the cycle time of the processor.   
     
     
       26. The system according to claim 25, wherein said designation circuit includes a memory for storing address information representing said first part of said nonvolatile memory, and comparison means for comparing address information output by said processor with the address information stored in said memory, and wherein the address information is set by performing a program on the processor. 
     
     
       27. The system according to claim 26, wherein each of said memory cells having a ferroelectric capacitor such that a nonvolatile storage operation is performed to each memory cell depending on the direction of the polarity of said ferroelectric capacitor.