Current steering circuit for a digital-to-analog converter

Abstract

An improved current steering cell for a DAC which eliminates the need for an inverter reduces the noise at the common mode. The cell includes a first and a second current steering MOS transistor of a first polarity type, each having a gate and a pair of current passing terminals. The cell has an input terminal for receiving digital input signals coupled to the gate of the first of the pair of current steering transistors, and a common mode node for receiving an input current coupled to the same one of the pair of current passing terminals of each current steering MOS transistor. The current output terminal of the cell is coupled to the other of the pair of current passing terminals of the first of the current steering MOS transistors. Finally, the cell includes a third MOS transistor of the opposite polarity type to the current steering MOS transistors, having a gate and a pair of current passing terminals for passing a current through the transistor, the gate of the third MOS transistor being coupled to the gate of the first MOS current steering transistor, and the current passing terminals of the third MOS transistor being coupled between the gate of the second MOS current steering transistor and one of the pair of current passing terminals of the second MOS current steering transistor.

What is claimed is: 
     
       1. A current steering circuit comprising: first and second current steering MOS transistors of a first polarity type, each having a gate and a pair of terminals for passing a current through the transistors,   an input terminal for receiving digital input signals coupled to the gate of the first of the pair of current steering transistors;   a common mode node for receiving an input current coupled to the same one of the pair of current passing terminals of each current steering MOS transistor;   a current output terminal coupled to the other of the pair of current passing terminals of the first of the current steering MOS transistors; and   a third MOS transistor of the opposite polarity type to the pair of current steering MOS transistors having a gate and a pair of terminals for passing a current through the transistor, the gate of the third MOS transistor being coupled to the gate of the first MOS current steering transistor and the terminals for passing a current through the third MOS transistor being coupled between the gate of the second MOS current steering transistor and, through a first resistor to one of the pair of terminals for passing a current through the second MOS current steering transistor, the first resistor having a resistance selected to match the output resistance seen by either of pair of the current steering MOS transistors.   
     
     
       2. The current steering circuit of claim 1 wherein the first and second current steering MOS transistors are P-channel and the third MOS transistor is N-channel. 
     
     
       3. The current steering circuit of claim 1 wherein the gate of the second MOS current steering transistor is coupled to a first point of fixed potential. 
     
     
       4. The current steering circuit of claim 1 having a pair of conductively biased, cascaded fourth and fifth MOS transistors coupled between a second point of fixed potential of opposite polarity to the first point of fixed potential and the common mode node, for passing current to the common mode node. 
     
     
       5. The current steering circuit of claim 4 wherein the fourth and fifth MOS transistors are the same polarity type as the first and second MOS current steering transistors. 
     
     
       6. The current steering circuit of claim 1 wherein the digital signals are input signals to a DAC. 
     
     
       7. A current steering circuit comprising: first and second current steering MOS transistors of a first polarity type, each having a gate and a pair of terminals for passing a current through the transistors,   an input terminal for receiving digital input signals to a DAC which has n input bits, the digital input signals being coupled to the gate of the first of the pair of current steering transistors;   a common mode node for receiving an input current coupled to the same one of the pair of current passing terminals of each current steering MOS transistor;   a current output terminal coupled to the other of the pair of current passing terminals of the first of the current steering MOS transistors; and   a third MOS transistor of the opposite polarity type to the pair of current steering MOS transistors having a gate and a pair of terminals for passing a current through the transistor, the gate of the third MOS transistor being coupled to the gate of the first MOS current steering transistor, and the terminals for passing a current through the third MOS transistor being coupled between the gate of the second MOS current steering transistor and, through a first resistor, to one of the pair of terminals for passing a current through the second MOS current steering transistor, the other of the pair of current passing terminals of the first of the current steering MOS transistors being for connection to a second resistor, the resistance value of the first resistor being 1/2×2 n  ×R, wherein n=the number of input bits to the DAC and R=the resistance value of the second resistor.   
     
     
       8. The current steering circuit of claim 7 wherein the first and second current steering MOS transistors are P-channel and the third MOS transistor is N-channel. 
     
     
       9. The current steering circuit of claim 7 wherein the gate of the second MOS current steering transistor is coupled to a first point of fixed potential. 
     
     
       10. The current steering circuit of claim 7 having a pair of conductively biased, cascaded fourth and fifth MOS transistors coupled between a second point of fixed potential of opposite polarity to the first point of fixed potential and the common mode node, for passing current to the common mode node. 
     
     
       11. The current steering circuit of claim 10 wherein the fourth and fifth MOS transistors are the same polarity type as the first and second MOS current steering transistors.