Generating pulses in analog channel of ATE tester

Abstract

A method simulating the filtering of a current pulse in a series of pulses. The method includes receiving a series of n+1 consecutive pulse addresses, including a pulse address for the current pulse as the last in the series of n+1, each pulse address being in a range of m values; storing the n pulses addresses prior to the current pulse address; building a composite address from the current pulse address and the prior n pulse addresses and applying the composite address to read a pulse shape from a memory of at least m n+1 pulse shapes. Also, apparatus issuing high speed pulses of programmable length. The apparatus includes a field of programmable memory to store a pulse length; a pulse clock line carrying a pulse clock signal having a pulse frequency; a frequency multiplier connected to receive the pulse clock signal and the pulse length stored in the programmable memory field and producing a sample clock signal having a frequency equal to the pulse length times the pulse clock frequency; a pulse memory holding the samples for a pulse; a DAC coupled to the pulse memory and generating analog pulses from samples received from the pulse memory; and a signal path carrying the sample clock signal to set the sampling frequency of a DAC and to clock samples from the pulse memory to the DAC.

What is claimed is: 
     
       1. A method simulating the filtering of a current pulse in a series of pulses, comprising: receiving a series of n+1 consecutive pulse addresses, including a pulse address for the current pulse as the last in the series of n+1, each pulse address being in a range of m values;   storing the n pulse addresses prior to the current pulse address;   building a composite address from the current pulse address and the prior n pulse addresses and applying the composite address to read a pulse shape from a memory of at least m n+  1 pulse shapes.   
     
     
       2. The method of claim 1 where n is selected from the group consisting of 1, 3, and 7; and   m n+1  is 2 16 .   
     
     
       3. The method of claim 1 where the memory of pulse shapes provides 10 or more sample points per pulse.   
     
     
       4. The method of claim 1 where the memory of pulse shapes provides 8 or more bits of resolution per sample point.   
     
     
       5. Apparatus generating sample points defining a pulse, comprising: address terminals carrying pulse addresses, each pulse address being in a range of m values;   a pulse memory coupled to the address terminals and storing the n most recent pulse addresses appearing on the address terminals prior to a current pulse address; and   a pulse shape memory having memory locations to store at least m n+1  pulse shapes and coupled to the pulse memory to receive a composite address input formed from the n most recent pulse addresses and the current pulse address.   
     
     
       6. The apparatus of claim 5 further comprising: address mode terminals carrying an address mode signal; where: the address mode terminals are coupled to the pulse memory and the pulse memory response to the address mode signal to determine the number n of pulse addresses to store.     
     
     
       7. The apparatus of claim 5 where n is selected from the group consisting of 1, 3, and 7; and   m n+1  is 2 16 .   
     
     
       8. The apparatus of claim 5 where the memory of pulse shapes memory locations store 10 or more sample points per pulse shape.   
     
     
       9. The apparatus of claim 5 where the memory locations of the memory of pulse shapes store 8 or more bits of resolution per sample point of a pulse shape.   
     
     
       10. Apparatus issuing high speed pulses of programmable length, comprising: a field of programmable memory to store a pulse length;   a pulse clock line carrying a pulse clock signal having a pulse frequency;   a frequency multiplier connected to receive the pulse clock signal and the pulse length stored in the programmable memory field and producing a sample clock signal having a frequency equal to the pulse length times the pulse clock frequency;   a pulse memory holding the samples for a pulse;   a DAC coupled to the pulse memory and generating analog pulses from samples received from the pulse memory; and   a signal path carrying the sample clock signal to set the sampling frequency of a DAC and to clock samples from the pulse memory to the DAC.   
     
     
       11. The apparatus of claim 10 where the DAC has a sampling frequency of at least 1 Gsps and a resolution of at least 8 bits. 
     
     
       12. The apparatus of claim 10 where the pulse length is selected from a group consisting of 3, 4, 5, 6, 7, 8, 10, 12, 14, and 16 samples per pulse. 
     
     
       13. The apparatus of claim 10 where the pulse frequency is in the range of 75 MHz to 400 MHz. 
     
     
       14. The apparatus of claim 10 further comprising: a set of pulse address input lines carrying pulse address signals synchronized to the pulse clock signal; and   an address generator circuit connected to the pulse address input lines and to the pulse memory and converting pulse addresses to addresses for the pulse shape memory.   
     
     
       15. A method issuing high speed pulses of programmable length, comprising: receiving a pulse length L;   receiving a sequence of pulse addresses;   selecting an addressable block of S pulse samples from a pulse sample memory according to an address built from N consecutive pulse addresses in the sequence, where N does not exceed S/L; and   transferring N×L pulse samples from the block to a high-speed DAC.   
     
     
       16. The method of claim 15 where the rate of transferring is at least 1 Gsps. 
     
     
       17. The method of claim 15 where the pulse length L is selected from a group consisting of 3, 4, 5, 6, 7, 8, 10, 12, 14, and 16 samples per pulse and the block size S is 16 samples. 
     
     
       18. The method of claim 15 where the ratio S:L is exactly 1, 2, or 4 and is equal to N. 
     
     
       19. The method of claim 15 further comprising: storing N samples of pulse length L in consecutive sample positions in an addressable block of the pulse sample memory before receiving the sequence of pulse addresses.   
     
     
       20. The method of claim 1, further comprising: receiving a next pulse address as the next consecutive pulse address after the series of n+1 consecutive pulse addresses;   storing the n consecutive pulse addresses received immediately prior to the receipt of the next pulse address;   building a next composite address from the next pulse address and the n pulse addresses received prior to the next pulse address and applying the next composite address to read a next pulse shape from the memory of pulse shapes.