Phase detector having a sampling circuit

Abstract

A phase detector enables sampling of an input waveform such that a resolution, equivalent to the resolution conventionally obtained by doubling a clock frequency, is obtained without doubling the frequency. In order to accomplish this, the phase detector has the following construction and function. A first sampling circuit samples an input waveform using an in-phase clock signal from a clock to generate a sampled waveform. A second sampling circuit samples the input waveform by using a falling edge of the clock to generate an output a signal. A third sampling circuit samples the output signal from the second sampling circuit by a rising edge of the sampled waveform supplied from the first sampling circuit to generate a phase detection flag. This phase detection flag thus detects the presence of the input waveform at a rate double the frequency of the clock.

What is claimed is: 
     
       1. A phase detector comprising: a first sampling circuit for sampling an input waveform by a clock of a specific period;   a second sampling circuit for sampling said input waveform by a clock of a phase reverse to that of said clock; and   a third sampling circuit for sampling an output signal from the second sampling circuit by an output from the first sampling circuit to produce a phase detection flag.   
     
     
       2. A phase detector comprising: a first sampling circuit for sampling an input waveform by a clock of a specific period;   a second sampling circuit for sampling said input waveform by a clock of a phase reverse to that of said clock;   a third sampling circuit for sampling an output signal from the second sampling circuit by an output from the first sampling circuit to produce a phase detection flag; and   the first through the third sampling circuits each are D-type flip-flops.   
     
     
       3. A phase detector as claimed in claim 1, wherein the first and the second sampling circuits each are latch circuits. 
     
     
       4. A phase detector as claimed in claim 1, wherein the third sampling circuit is a D-type flip-flop. 
     
     
       5. A phase detector comprising: a first sampling circuit for sampling an input waveform using a clock having a specific period;   a second sampling circuit for sampling said input waveform by inverting a signal from said clock; and   a third sampling circuit using an output from said first sampling circuit for sampling an output signal from said second sampling circuit to produce a phase detection output.   
     
     
       6. A phase detector as claimed in claim 5, wherein said inverted signal of said second sampling circuit has a phase inverse to that of said clock of said first sampling circuit. 
     
     
       7. A phase detector as claimed in claim 5, wherein said third sampling circuit is a D-type flip-flop. 
     
     
       8. A phase detector as claimed in claim 5, wherein said first through said third sampling circuits each are D-type flip-flops. 
     
     
       9. A phase detector as claimed in claim 5, wherein said first and said second sampling circuits are each latch circuits.