Fast clock generator and clock synchronizer for logic derived clock signals with synchronous clock suspension capability for a programmable device

Abstract

A programmable device includes a circuit for generating an asynchronous logic derived clock signal derived from one or more of a number of input signals. Circuits for synchronizing the asynchronous logic derived clock signal to a reference clock signal are coupled to the circuit for generating the asynchronous logic derived clock signal. The circuits for synchronizing generate a synchronized logic derived clock signal from the asynchronous clock signal and a reference clock signal. The programmable device further includes a circuit for suspending a clock signal. In one embodiment, a logic derived clock signal is generated and synchronized with a synchronous clock signal. In synchronizing the logic derived clock signal an intermediate signal is generated during a first clock cycle of the synchronous clock signal and is combined with the synchronized logic derived clock signal during a second clock cycle of the synchronous clock signal to produce a suspendable clock signal. The suspendable clock signal may be gated off in response to an input signal having a minimum duration of at least two clock cycles of the synchronous clock signal.

I claim: 
     
       1. A method of suspending a clock signal in a programmable device comprising the steps of: generating an asynchronous logic derived clock signal from one or more input signals;   synchronizing said asynchronous logic derived clock signal with a synchronous clock signal provided to said programmable logic device by: producing a first intermediate signal from said asynchronous logic derived clock signal at a first clock cycle of said synchronous clock signal,   producing a synchronized logic derived clock signal from said first intermediate signal at a second clock cycle of said synchronous clock signal;     combining said first intermediate signal with said synchronized logic derived clock signal during said second clock cycle of said synchronous clock signal to produce a second intermediate signal; and   combining said second intermediate signal with said synchronous clock signal during said second clock cycle to produce a suspendable clock signal.   
     
     
       2. A method as in claim 1 wherein said step of combining said second intermediate signal with said synchronous clock signal comprises producing a signal which is the result of a logical AND operation between said second intermediate signal and said synchronous clock signal, said signal being said suspendable clock signal. 
     
     
       3. A method as in claim 2 wherein said suspended clock signal is gated off when said asynchronous logic derived clock signal is asserted for at least two clock cycles of said synchronous clock signal. 
     
     
       4. A method as in claim 3 wherein said first intermediate signal is produced using a first D-type data register which captures a logic state of said asynchronous logic derived clock signal in response to a first rising edge of said synchronous clock signal. 
     
     
       5. A method as in claim 4 wherein said synchronized logic derived clock signal is produced using a second D-type data register which captures a logic state of said first intermediate signal in response to a next rising edge of said synchronous clock signal. 
     
     
       6. A method as in claim 5 wherein said step of combining said first intermediate signal with said synchronized logic derived clock signal comprises using a third D-type data register to capture a logic state of a signal which is a logical NAND of said first intermediate signal and said synchronized logic derived clock signal. 
     
     
       7. A device, comprising: means for generating an asynchronous logic derived clock signal from one or more of a plurality of input signals;   means for synchronizing said asynchronous logic derived clock signal to a reference clock signal to generate a synchronized logic derived clock signal coupled to said means for generating; and   means for suspending said synchronized logic derived clock signal in response to said input signals.   
     
     
       8. A device as in claim 7 wherein said means for generating an asynchronous logic derived clock signal comprises an asynchronous clock logic array coupled to at least one of said plurality of input signals and adaptable to provide at least one of a sum of products term, a sum term or a product term combining any subset or all of said plurality of input signals to generate said asynchronous logic derived clock signal. 
     
     
       9. A device as in claim 8 wherein said means for synchronizing comprises a series coupled register pair configured to receive said asynchronous logic derived clock signal as an input and to generate said synchronized logic derived clock signal as an output in response to said reference clock signal. 
     
     
       10. A device as in claim 9 wherein said series coupled register pair comprises two D-type data registers. 
     
     
       11. A device as in claim 9 wherein said means for synchronizing further comprises a synchronous clock select multiplexer coupled to receive a plurality of external synchronous clock signals and to provide one of said plurality of synchronous clock signals as said reference clock signal to said series coupled register pair. 
     
     
       12. A method of generating a synchronized logic derived clock signal in a programmable device comprising the steps of: generating an asynchronous logic derived clock signal from one or more of a plurality of input signals;   synchronizing said asynchronous logic derived clock signal to a reference clock signal to produce a synchronized logic derived clock signal; and   suspending said synchronized logic derived clock signal in response to said input signals and said reference clock signal.   
     
     
       13. A method of generating a synchronized logic derived clock signal as in claim 12 wherein said step of synchronizing comprises the steps of: capturing said asynchronous logic derived clock signal in a first register on a first clock cycle of said reference clock signal to produce an intermediate signal; and   capturing said intermediate signal in a second register on a subsequent clock cycle of said reference clock cycle to produce said synchronized logic derived clock signal.   
     
     
       14. A method of generating a synchronized logic derived clock signal as in claim 13 wherein said reference clock signal has a minimum clock period of at least the sum of a first delay period associated with said step of generating said asynchronous logic derived clock signal and a second delay period required to ensure capture of a valid signal in said first register during said step of capturing said asynchronous clock signal. 
     
     
       15. A circuit, comprising: an asynchronous clock logic array configured to generate an asynchronous logic derived clock signal from one or more input signals;   a clock synchronizer configured to synchronize said asynchronous logic derived clock signal to a reference clock signal to produce a synchronized logic derived clock signal; and   a clock suspension circuit configured to receive said synchronized logic derived clock signal, said reference clock signal and an intermediate signal produced by said clock synchronizer in the process of producing said synchronized logic derived clock signal and to generate a suspended clock signal therefrom in response to an input signal having at least a minimum duration of two clock cycles of said reference clock signal.   
     
     
       16. A circuit as in claim 15 wherein said clock suspension circuit includes an AND gate, an output of which is said suspended clock signal. 
     
     
       17. A circuit of suspending a clock signal in a programmable device comprising: means for generating an asynchronous logic derived clock signal from one or more input signals;   means for synchronizing said asynchronous logic derived clock signal with a synchronous clock signal provided to said programmable logic device by: means for producing a first intermediate signal from said asynchronous logic derived clock signal at a first clock cycle of said synchronous clock signal,   means for producing a synchronized logic derived clock signal from said first intermediate signal at a second clock cycle of said synchronous clock signal;   means for combining said first intermediate signal with said synchronized logic derived clock signal during said second clock cycle of said synchronous clock signal to produce a second intermediate signal; and   means for combining said second intermediate signal with said synchronous clock signal during said second clock cycle to produce a suspendable clock signal.     
     
     
       18. A circuit as in claim 17 wherein said means for combining said second intermediate signal with said synchronous clock signal further comprises means for producing a signal which is the result of a logical AND operation between said second intermediate signal and said synchronous clock signal, said signal being said suspendable clock signal. 
     
     
       19. A circuit as in claim 18 wherein said suspended clock signal is gated off when said asynchronous logic derived clock signal is asserted for at least two clock cycles of said synchronous clock signal. 
     
     
       20. A circuit as in claim 19 wherein said first intermediate signal is produced using a first D-type data register which captures a logic state of said asynchronous logic derived clock signal in response to a first rising edge of said synchronous clock signal.