Method and apparatus for power management

Abstract

An apparatus includes a first register having a first field that stores a first value that indicates a power management state of a bus. A bus regulator is coupled to the first register. The bus regulator regulates the bus according to the power management state.

What is claimed is: 
     
       1. An apparatus, comprising: a first register having a first field that stores a first value that indicates a power management state of a bus that is based on a second value that indicates a power management state of a component coupled to the bus; and   a bus regulator, coupled to the first register, that regulates the bus according to the power management state.   
     
     
       2. The apparatus of claim 1, wherein the bus regulator is a clock regulator that adjusts a speed of the bus according to the power management state. 
     
     
       3. The apparatus of claim 1, wherein the bus regulator is a power regulator that adjusts power to the bus according to the power management state. 
     
     
       4. The apparatus of claim 1, further comprising a second register having a second field that stores a third value that indicates power management states that the apparatus supports. 
     
     
       5. The apparatus of claim 4, further comprising a third register having a third field that stores a fourth value that indicates whether bus regulating functions to the bus are enabled/disabled. 
     
     
       6. A computer system, comprising: a first bus;   a processor coupled to the first bus;   a second bus;   an apparatus, coupled to the first and second bus, including a first register having a first field that stores a first value that indicates a power management state of the second bus that is based on a second value that indicates a power management state of a component coupled to the second bus, and a bus regulator, coupled to the first register, that regulates the second bus according to the power management state.   
     
     
       7. The computer system of claim 6, wherein the bus regulator is a clock regulator that adjusts a speed of the second bus according to the power management state. 
     
     
       8. The computer system of claim 6, wherein the bus regulator is a power regulator that adjusts power to the second bus according to the power management state. 
     
     
       9. The computer system of claim 6, further comprising a second register having a second field that stores a third value that indicates power management states that the apparatus supports. 
     
     
       10. The computer system of claim 9, further comprising a third register having a third field that stores a fourth value that indicates whether bus regulating functions to the bus are enabled/disabled. 
     
     
       11. An apparatus, comprising: means for storing a first value that indicates a power management state of a bus that is based on a second value that indicates a power management state of a component coupled to the bus; and   means for regulating the bus according to the power management state.   
     
     
       12. A method for managing a bus, comprising: assigning a first power management state to a first function of a component connected to the bus;   assigning a second power management state to an originating device of the bus based on the first power management state; and   regulating the bus to the second power management state assigned to the originating device.   
     
     
       13. The method of claim 12, wherein the step of assigning the power management state to the originating device comprises assigning to the originating device a power management state belonging to a most active function on the bus. 
     
     
       14. The method of claim 12, wherein the step of regulating the bus to the power management state assigned to the originating device comprises instructing a bus regulator on the originating device to regulate the bus. 
     
     
       15. The method of claim 12, further comprising the step of: preparing the first function for transitioning into the first power management state;   regulating the first function to the first power management state; and   writing a value in a register corresponding to the first function that indicates that the first function is in the first power management state.   
     
     
       16. The method of claim 12, further comprising the step of writing a value in a register corresponding to the originating device that indicates that the originating device is to be put in the second power management state. 
     
     
       17. A computer-readable medium having stored thereon sequences of instructions, the sequences of instructions including instructions which, when executed by a processor, causes the processor to perform the steps of: assigning a first power management state to a first function of a component connected to a bus;   assigning a second power management state to an originating device of the bus based on the first power management state; and   regulating the bus to the second power management state assigned to the originating device.   
     
     
       18. The computer-readable medium of claim 17, wherein the step of assigning the power management state to the originating device comprises assigning to the originating device a power management state belonging to a most active function on the bus.