Repairing fractured wafers in semiconductor manufacturing

Abstract

The specification describes a technique for repairing wafer fractures that occur during wafer fabrication. The fractured pieces are joined edge-to-edge at the fracture line and bonded with epoxy adhesive. The method succeeds because the dimensions of the fracture line after bonding is within the reregistration tolerance of commercial step-and-repeat cameras and the reregistration capability of the camera allows normal exposure of sites that do not intersect the fracture line.

We claim: 
     
       1. Method for the manufacture of semiconductor wafers in which the semiconductor wafers have a multiplicity of IC device sites arranged in a pattern on the semiconductor wafer, and each of said IC device sites has a set of alignment marks, the method comprising: a. passing the semiconductor wafer being fabricated through a sequence of wafer fabrication steps in a processing line, said steps including a multiplicity of step and repeat lithography steps, said step and repeat lithography steps comprising exposing each IC site to a lithographic pattern using a step and repeat camera, and aligning the lithographic mask to each IC chip site using said alignment marks,   b. removing a fractured wafer from said processing line after exposure of said wafer to at least one step and repeat lithography step, said fractured wafer consisting of at least two pieces with each of said pieces having a fracture edge corresponding to the fracture line of said wafer, and said fracture line intersecting a multiplicity of said IC device sites,   c. applying an adhesive material to the said fracture edge of at least one of said pieces,   d. placing said pieces together with said fracture edges in contact,   e. aligning said fracture edges,   f. curing said adhesive material to produce a repaired wafer,   g. reinserting said repaired wafer into said processing line, and   h. exposing said repaired wafer to at least one of said step and repeat lithography steps.   
     
     
       2. The method of claim 1 in which the step and repeat lithography steps are photolithography steps. 
     
     
       3. The method of claim 1 in which the step and repeat steps are selected from the group consisting of e-beam and x-ray lithography. 
     
     
       4. The method of claim 1 in which the semiconductor wafer is a III-V semiconductor wafer. 
     
     
       5. The method of claim 4 in which the semiconductor wafer is selected from the group consisting of InP, GaAs, and combinations thereof. 
     
     
       6. The method of claim 1 in which the adhesive material is epoxy. 
     
     
       7. The method of claim 1 in which the fractured wafer consists of two pieces. 
     
     
       8. The method of claim 1 in which the sequence of fabrication steps is at least 25% complete when the fractured wafer is removed from the processing line. 
     
     
       9. The method of claim 5 in which the said IC devices in the said IC device sites are double heterostructure bipolar transistors. 
     
     
       10. The method of claim 1 wherein the repaired wafer has the same thickness as the original wafer. 
     
     
       11. The method of claim 1 including the additional step, after step b, of coating at least one surface of each of the said pieces with photoresist, and removing the photoresist after step f. thereby lifting off excess adhesive material from said surface. 
     
     
       12. Method for the manufacture of hybrid semiconductor wafers in which the hybrid semiconductor wafers comprise a section of a first semiconductor material adjacent to a section of a second semiconductor material, wherein said first and second semiconductor materials are different, said hybrid semiconductor wafer having a multiplicity of IC device sites arranged in a pattern on the semiconductor wafer, with each of said IC device sites including a section of said first semiconductor material and a section of said second semiconductor material, the method comprising: a. scribing a first section of semiconductor material from a first semiconductor wafer to produce a first scribed semiconductor section having a scribed edge,   b. scribing a second section of semiconductor material from a second semiconductor wafer to produce a second scribed semiconductor section having a scribed edge, said first and second semiconductor wafers consisting of different semiconductor materials,   c. applying an adhesive material to the said scribed edge of said first one of said scribed semiconductor sections,   d. placing said first and second scribed semiconductor sections together with said scribed edges in contact, and   e. curing said adhesive material to produce said hybrid semiconductor wafer.   
     
     
       13. The method of claim 12 further including passing said hybrid semiconductor wafer through a sequence of wafer fabrication steps in a processing line, said steps including a multiplicity of step and repeat lithography steps, said step and repeat lithography steps comprising exposing each IC site to a lithographic pattern that exposes simultaneously at least a portion of said first and second scribed semiconductor sections. 
     
     
       14. The method of claim 12 in which adhesive material is applied to both of said scribed edges. 
     
     
       15. The method of claim 12 in which the adhesive material is epoxy. 
     
     
       16. The method of claim 12 in which the said first semiconductor materials is GaAs. 
     
     
       17. The method of claim 12 in which the said first semiconductor material is InP. 
     
     
       18. The method of claim 16 in which the said second semiconductor material is InP. 
     
     
       19. The method of claim 12 in which the said scribed sections are formed by scribing along scribe lines corresponding to chords of said wafers. 
     
     
       20. The method of claim 19 in which at least two chords of a semiconductor wafer are scribed to form at least two of said scribed semiconductor sections and the two scribed semiconductor sections are used to form two different hybrid semiconductor wafers. 
     
     
       21. The method of claim 12 in which said first and second semiconductor wafers and said hybrid semiconductor wafer have essentially the same shape and dimensions.