Phase locked loop circuit with reduced electrical power consumption

Abstract

A phase lock loop circuit includes a phase detector for receiving a reference clock and a feedback clock, a charge pump for receiving a Down pulse and an Up pulse from the phase detector, a loop filter for being charged and discharged by the output from the charge pump, and a voltage controlled oscillator for outputting a frequency signal according to the output voltage of the loop filter, the phase detector including a power cut input terminal, and when a power cut signal is input to the power cut input terminal, a Down pulse and an Up pulse output from the phase detector are forcibly changed to logic "L" level and logic "H" level, respectively, which reduces the power consumption in the phase locked loop circuit.

What is claimed is: 
     
       1. A phase locked loop circuit comprising: a phase detector receiving a reference clock, a feedback clock, and a power cut signal and generating Up pulses and Down pulses according to relative phases of the reference clock and the feedback clock;   a charge pump receiving the Down pulses and the Up pulses from the phase detector;   a loop filter charged and discharged by an output from the charge pump and generating an output voltage in response to charging and discharging of the loop filter;   a voltage controlled oscillator outputting a frequency signal having a frequency determined by the output voltage of the loop filter; and   a frequency divider for dividing the frequency signal from the voltage controlled oscillator to produce the feedback clock supplied to the phase detector, wherein the phase detector comprises: a clock terminal receiving the reference clock;   a feedback clock terminal receiving the feedback clock;   a plurality of 2-input NAND circuits, a first group of the 2-input NAND circuits being connected in series, one of the 2-input NAND circuits of the first group receiving the reference clock, the first group of 2-input NAND circuits outputting a first output signal, and a second group of the 2-input NAND circuits being connected in series, one of the 2-input NAND circuits of the second group receiving the feedback clock, the second group of 2-input NAND circuits outputting a second output signal;   a NOR circuit coupled to the first and second output signals of the first and second groups of 2-input NAND circuits;   a first inverter inverting an output signal from the NOR circuit;   first and second multiple input NAND circuits respectively receiving the first and second output signals from the first and second groups of the 2-input NAND circuits, both of the first and second multiple input NAND circuits receiving output signals from the first inverter and the power cut signal;   a second inverter connected to an output terminal of the first multiple input NAND circuit;   a Down terminal connected to an output terminal of the second inverter for outputting the Down pulses; and   an Up terminal connected to an output terminal of the second multiple input WAND circuit for outputting the Up pulses, wherein the phase detector changes the Down pulses and the Up pulses, respectively, to opposite logic levels, in response to the power cut signal supplied to the first and second multiple input NAND circuits.     
     
     
       2. A phase locked loop circuit comprising: a phase detector receiving a reference clock, a feedback clock, and a power cut signal and generating Up pulses and Down pulses according to relative phases of the reference clock and the feedback clock;   a charge pump receiving the Down pulses and the Up pulses from the phase detector;   a loop filter charged and discharged by an output from the charge pump and generating an output voltage in response to charging and discharging of the loop filter;   a voltage controlled oscillator outputting a frequency signal having a frequency determined by the output voltage of the loop filter; and   a frequency divider for dividing the frequency signal from the voltage controlled oscillator to produce the feedback clock supplied to the phase detector, wherein the phase detector comprises: a clock terminal for receiving the reference clock;   a feedback clock terminal for receiving the feedback clock; a main frame portion comprising,   a plurality of 2-input NAND circuits, a first group of the 2-input NAND circuits being connected in series, one of the 2-input NAND circuits of the first group receiving the reference clock, the first group of 2-input NAND circuits outputting a first output signal, and a second group of the 2-input NAND circuits being connected in series, one of the 2-input NAND circuits of the second group receiving the feedback clock, the second group of 2-input NAND circuits outputting a second output signal;   a NOR circuit coupled to the first and second output signals of the first and second groups of 2-input NAND circuits;   a first inverter inverting an output signal from the NOR circuit;   first and second multiple input NAND circuits respectively receiving the first and second output signals from the first and second groups of the 2-input NAND circuits, both of the first and second multiple input NAND circuits receiving output signals from the first inverter;   a second inverter connected to an output terminal of the first multiple input NAND circuit;   a first 2-input NAND circuit having a first input terminal connected to an output of the second inverter and a second input terminal connected to the power cut signal;   a third inverter having an input connected to an output terminal of the second multiple input NAND circuit;   a second 2-input NAND circuit having a first input terminal connected to an output of the third inverter and a second input terminal connected to the power cut signal;   a fourth inverter having an input terminal connected to an output terminal of the first 2-input NAND circuit;   a Down terminal connected to an output terminal of the fourth inverter for outputting the Down pulses; and   an Up terminal connected to an output terminal of the second 2-input NAND circuit for outputting the Up pulses, wherein the phase detector changes the Down pulses and the Up pulses, respectively, to opposite logic levels, in response to the power cut signal supplied to the second input terminals of the first and second 2-input NAND circuits.