Incremental bus reconfiguration without bus resets

Abstract

An electronic system interconnect. The interconnect comprises a first node and a second node coupled to the first node. The interconnect is initially configured to include the first and second nodes. A third node is added to the interconnect after the interconnect is initially configured, and the first node responds to the addition of the third node by initiating a new connect handshake with the third node. The first node begins by transmitting a first signal to the third node. The first node signals that the third node has been added to the interconnect if the third node responds to the first signal by transmitting a second signal. The first node causes the interconnect to be reconfigured if the third node transmits a third signal in response to receiving the first signal.

What is claimed is: 
     
       1. A node for use in an electronic system interconnect comprising: at least one port including a first port operative to transmit and receive data when electrically connected to another node;   a first circuit coupled to the first port operative to detect when an electrical connection is made between the first port and a second node; and   a second circuit coupled to the first port operative to detect how many ports are connected to transmit and receive data after the electrical connection is made between the first port and the second node,   wherein the node is operative to initiate a new connect handshake with the second node by transmitting a first signal via the first port if the node has more than one connected port, the node being operative to wait for the second node to initiate the new connect handshake by transmitting the first signal to the node if the node has only one connected port, the node transmitting a reset request if the node and the second node contemporaneously assert the first signal, and   wherein the node transmits a second signal in response to receiving the first signal, the second signal completing the new connect handshake, thereupon the second node is added to the interconnect without requiring a reset request by the first node, the second node being assigned a bus address after the assumption of a temporary address.   
     
     
       2. The node claimed in claim 1, wherein the node transmits a reset request if the node waits a predetermined time before receiving the first signal from the second node. 
     
     
       3. The node as claimed in claim 1, wherein the interconnect is a serial bus.