Method and apparatus for internally caching the minimum and maximum XY pixel address values in a graphics subsystem

Abstract

A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes a XY address for rendering the graphics primitives. A graphics processor which includes an address tracking logic circuit tracks the rendering primitive to determine the minimum and maximum XY addresses of the rendered primitive. By tracking of the XY address, the graphics processor is able to internally cache only modified portions of the rendered primitive thereby improving the graphics processor's access cycle to the modified data. Accordingly, the graphics processor's memory bandwidth requirements is reduced.

What is claimed is: 
     
       1. A system for caching graphics primitives into an internal storage space to provide a fast retrieval operation to render the graphics primitive, wherein the minimum and maximum addresses responsive to the width and length values of the primitive is tracked to determine when to overwrite the internal storage unit, the system comprising: a system bus for communicating data and instructions and generating address write cycles;   a host processor coupled to the system bus for generating graphics primitive address requests to the system bus;   a system memory coupled to the system bus for storing a list of display parameters responsive to the graphics primitives;   a graphic subsystem coupled to the system bus for processing the graphics primitives address request generated by the host processor and rendering the graphics primitives;   an internal storage unit disposed within the graphic subsystem for temporarily storing XY pixel addresses cached in the graphic subsystem; and   a memory interface control unit coupled to the graphic subsystem for asserting control signals to allow the graphic subsystem to interpolate a polygon from a main storage unit and the internal storage unit, wherein the graphic subsystem includes means to track minimum and maximum XY addresses of a modified portion of the polygon, and wherein the modified portion of the polygon is stored in the internal storage unit in response to the maximum and minimum XY addresses.   
     
     
       2. The system of claim 1, wherein the main storage unit is a frame buffer. 
     
     
       3. The system of claim 2, wherein the addresses stored in the internal storage unit are relative addresses of the addresses stored in the main storage unit. 
     
     
       4. The system of claim 3, wherein the internal storage unit is a static random access memory (SRAM) unit. 
     
     
       5. The system of claim 4, wherein the host processor provides signals to initiate a fetch request operation to fetch the addresses corresponding to the polygon being rendered from the frame buffer. 
     
     
       6. The system of claim 5, wherein the graphic subsystem includes means to generate XY addresses in the main storage unit in response to the maximum and minimum XY addresses. 
     
     
       7. The system of claim 6, wherein the memory controller includes means of determining the storing sequence of the pixel addresses for the polygon stored in the internal storage unit. 
     
     
       8. The system of claim 7, wherein the means for determining the storing sequence is a storing state machine. 
     
     
       9. The system of claim 8 further including a means of tracking fetch sequences of pixel addresses for the polygon being rendered in the graphics subsystem. 
     
     
       10. The system of claim 9, wherein the means of tracking the fetch sequence is a fetch state machine. 
     
     
       11. A graphics processor for tracking the minimum and maximum XY pixel addresses of a polygon being rendered into a temporary storage space, the graphics processor comprising: a three dimensional (3D) engine for rendering polygons;   a tracking logic unit coupled to the 3D engine for tracking the minimum and maximum XY pixel addresses of a rendered polygon;   an address recalculation unit coupled to the tracking logic unit to receive the minimum and maximum XY pixel addresses of the rendered polygon to generate new address values for the minimum and maximum pixel addresses for modified portions of the rendered polygon; and   an internal storage unit coupled to the tracking logic unit to temporarily store portions of the rendered polygon from a main storage unit.   
     
     
       12. The graphics processor of claim 11, wherein the XY pixel addresses respectively represent the width and length values of the polygon being rendered. 
     
     
       13. The graphics processor of claim 12, further including an address generating logic to generate relative XY pixel reference addresses corresponding to portions of the polygon stored in the main storage unit for storage in the temporary storage unit. 
     
     
       14. The graphics processor of claim 13, wherein the temporary storage unit is a static random access memory (SRAM) cache. 
     
     
       15. The graphics processor of claim 14, wherein the SRAM cache is 128 bytes wide. 
     
     
       16. The graphics processor of claim 14, wherein the SRAM cache is 256 bytes wide. 
     
     
       17. The graphics processor of claim 11, wherein the address recalculation unit includes a plurality of address comparators for receiving initial XY addresses and minimum and maximum XY addresses respectively, said address comparators generating a recalculated X or Y start address and an X or Y address extent. 
     
     
       18. The graphics processor of claim 17, wherein the recalculation unit recalculates the X or Y start address by adding the X or Y minimum address to the X or Y start address to move the starting point of an XY block of data in the internal storage unit. 
     
     
       19. The graphics processor of claim 11, wherein the tracking logic unit includes a minimum address tracking logic. 
     
     
       20. The graphics processor of claim 19, wherein the minimum address tracking logic includes a load register for holding current minimum XY addresses in the internal storage unit. 
     
     
       21. The graphics processor of claim 20, wherein the minimum address tracking logic further includes a plurality of AND gates for receiving a write enable signal which when asserted enables the load register to be loaded with the current XY minimum address. 
     
     
       22. The graphics processor of claim 21, wherein the minimum address tracking logic further includes a plurality of address comparators for comparing incoming minimum XY addresses with the XY minimum addresses stored in the load register and, wherein if the incoming minimum address is less than the stored minimum address the load register is overwritten with the incoming minimum address. 
     
     
       23. The graphics processor of claim 11, wherein the tracking logic unit further includes a maximum address tracking logic. 
     
     
       24. The graphics processor of claim 23, wherein the maximum address tracking logic includes a load register for holding current maximum XY addresses in the cache. 
     
     
       25. The graphics processor of claim 23, wherein the maximum address tracking logic further includes a plurality of AND gates for receiving a write enable signal which when asserted enables the load register to be loaded with the current XY maximum address. 
     
     
       26. The graphics processor of claim 23 wherein the maximum address tracking logic includes a plurality of address comparators for comparing incoming maximum XY addresses with stored maximum XY addresses in the load register, and wherein if the incoming maximum address is greater than the stored maximum address the load register is cleared to zero. 
     
     
       27. A method for tracking a minimum and maximum XY addresses of a polygon being rendered, comprising: generating a list of XY addresses to define the polygon to be tracked:   storing the XY addresses in an internal cache;   tracking the XY addresses in the internal cache when portions of the polygon being rendered are modified; and   overwriting the modified portion of the polygon in the internal cache when the maximum and the minimum XY addresses change.   
     
     
       28. The method of claim 27 including the step of comparing a depth value corresponding to the XY addresses of the polygon being rendered with a previous depth value to determine if the polygon should be overwritten. 
     
     
       29. The method of claim 27 further including the step of recalculating new XY address values in the main storage unit of the polygon as portions of the polygon are modified. 
     
     
       30. The method of claim 29, wherein said recalculating step includes the step of comparing incoming XY address values with stored XY address values to determine whether the rendered polygon has been modified. 
     
     
       31. The method of claim 30, wherein the recalculating step further includes the step of comparing an alpha blending parameter corresponding to the XY minimum and maximum XY addresses value with a previous alpha blending parameter of the polygon being rendered to determine whether to overwrite the polygon.