Method for manufacturing a circuit on a circuit substrate

Abstract

A frequency dependent lossy line subcircuit element has a first port (100), a second port (101), and a reference point (102). The lossy line element is configured to represent circuit performance over a band of frequencies. The lossy line element is modeled as a subcircuit comprising a parallel combination network of resistors (11-14), each with an inductor (1-4) in series disposed between the first port (100) and an internal node (103). Inductors (1-4) are proportioned in value relative to each other so as to control the magnitude of the simulated current flow through resistors (11-14) as a function of frequency content of an excitation signal appearing at the first port (100). The subcircuit, therefore, models frequency dependent attenuation for each frequency included in the range. A lossless transmission element (35) is further included in the frequency dependent lossy line subcircuit interposed between the internal node (103) and the second port (101) to represent the lossy line section delay and characteristic impedance of the transmission line.

I claim: 
     
       1. A method for fabricating an interconnection path comprising the steps of: providing a computer system for modeling performance of the interconnection path using a computer model,   selecting a set of application specific parameters for the computer model,   executing the computer model to simulate performance of said interconnection path in response to an excitation signal wherein the computer model comprises a subcircuit to simulate the interconnection path, the subcircuit comprising a dc resistance in series with a dc inductance, in parallel with a first frequency resistor in series with a first frequency inductor, said first frequency resistor and inductor series combination having a path to a reference point through a first frequency shunt capacitor,   comparing the simulation results against operational performance targets, modifying the set of application specific parameters and repeating the step of executing the computer model if the simulated results are not optimal,   fabricating the interconnection path according to an optimal one of said application specific parameter sets.   
     
     
       2. A method for fabricating an interconnection path as recited in claim 1 the computer model further comprising a second frequency resistor in series with a second frequency inductor in parallel with the first frequency resistor and inductor, said second frequency resistor and inductor series combination having a path to said reference point through a second frequency shunt capacitor. 
     
     
       3. A method for fabricating an interconnection path as recited in claim 2 the computer model further comprising a second frequency shunt resistor in series with the second frequency shunt capacitor. 
     
     
       4. A method for fabricating an interconnection path as recited in claim 2 the computer model further comprising a third frequency resistor in series with a third frequency inductor in parallel with the first frequency resistor and inductor, said third frequency resistor and inductor series combination having a path to said reference point through a third frequency shunt capacitor. 
     
     
       5. A method for fabricating an interconnection path as recited in claim 4 the computer model further comprising a third frequency shunt resistor in series with the third frequency shunt capacitor. 
     
     
       6. A method for fabricating an interconnection path as recited in claim 1 wherein the model further comprises a section delay element in series with said parallel combination network. 
     
     
       7. A method for fabricating an interconnect path based upon predicted frequency dependent performance of the interconnect path comprising the steps of: selecting a material, cross sectional measurements, and a length for the interconnect path,   selecting a first frequency,   determining values for the effective DC and first frequency resistance and effective DC and first frequency inductance from known resistive and inductive values per unit length having the selected cross sectional measurements for the material selected and from the total length of the interconnect path,   providing a computer model of at least a subcircuit representing the interconnect path, the subcircuit comprising a DC series combination of a DC resistance in series with a DC inductance, the DC series combination in parallel with a first frequency series combination of a first frequency resistance in series with a first frequency inductance, the first frequency series combination also including a first shunt path to a reference point through first frequency shunt capacitor,   calculating a skin depth at the first frequency,   determining values for the first frequency resistance and the first frequency inductance from known resistive and inductive values per unit length of the selected material having the cross sectional measurements, the calculated skin depth, and the length of the interconnect path,   determining a value for the first shunt capacitor from known capacitive values per unit length having the selected material, the cross sectional measurements, and the length of the interconnect path,   solving the computer model with the determined values to predict frequency dependent performance of the interconnect path, and   fabricating the interconnection path according to the selected materials.   
     
     
       8. A method for fabricating an interconnect path as recited in claim 7 wherein the computer model further comprises a second frequency series combination in parallel with said DC and first frequency series combinations, the second series combination including a second shunt path to the reference point through second frequency shunt capacitor and further comprising the steps of: selecting a second frequency,   determining values for the effective second frequency resistance and effective second frequency inductance from the known resistive and inductive values per unit length of the selected material having the selected cross sectional measurements, the calculated skin depth, and the length of the interconnect path,   determining a value for the second shunt capacitor from the known capacitive values per unit length of the selected material having the cross sectional measurements, and the length of the interconnect path.   
     
     
       9. A method for fabricating an interconnect path as recited in claim 8 wherein the computer model further comprises a third frequency series combination in parallel with said DC series combination, said first frequency series combination, and said second series combination, the third series combination also including a third shunt path to the reference point through third frequency shunt capacitor and further comprising the steps of: selecting a third frequency,   determining values for the effective third frequency resistance and effective third frequency inductance from the known resistive and inductive values per unit length of the selected material having the selected cross sectional measurements, the calculated skin depth, and the length of the interconnect path,   determining a value for the third shunt capacitor from the known capacitive values per unit length of the selected material having the cross sectional measurements, and the length of the interconnect path.   
     
     
       10. A method for fabricating an interconnect path as recited in claim 7 wherein the interconnect path has a first port, a second port, and the step of determining values for said DC resistance, said DC inductance, said first frequency resistance and said first frequency inductance comprises the step of proportioning said values relative to each other so as to control the magnitude of the simulated current flow through the interconnect path as a function of the frequency content of an excitation signal presented at said first port. 
     
     
       11. A method for fabricating an interconnect path as recited in claim 7 wherein the step of determining values for said DC resistance, said DC inductance, said first frequency resistance, and said first frequency inductance further comprises selecting a DC to first frequency resistance ratio constant and a DC to first frequency inductance ratio constant and iteratively solving for said DC resistance and inductance and said first frequency resistance and inductance to fit circuit combination impedances to the predetermined effective DC resistance and inductance and effective first frequency resistance and inductance. 
     
     
       12. A method for fabricating an interconnect path as recited in claim 8 and further comprising the step of determining values for said DC, first frequency, and second frequency resistances and DC, first frequency, and second frequency inductances by identifying the effective DC, first, and second resistances and selecting DC, first frequency, and second frequency resistance ratio constants and DC, first frequency, and second frequency inductance ratio constants and iteratively solving for said DC, first frequency, and second frequency resistances and said DC, first frequency, and second frequency inductances to fit the circuit combination impedance to the predetermined effective DC, first, and second resistances and inductances based upon the DC, first frequency, and second frequency resistance and inductance ratios. 
     
     
       13. A method for fabricating an interconnect path as recited in claim 9 wherein the step of determining values for said DC resistance, said DC inductance, said first frequency resistance, and said first frequency inductance further comprises selecting a DC, first frequency, second frequency, and third frequency resistance ratio constant and a DC, first frequency, second frequency, and third frequency inductance ratio constant and iteratively solving for said DC resistance and inductance, said first frequency resistance and inductance, said second frequency resistance and inductance, and said third frequency resistance and inductance to fit the circuit combination impedance to the predetermined effective DC, first frequency, second frequency, and third frequency resistance and effective DC, first frequency, second frequency, and third frequency inductance. 
     
     
       14. A method for fabricating on interconnect path as recited in claim 7 wherein the known resistive value per unit length of the selected material comprises an effective DC resistance and an effective AC resistance, assumption that all conduction occurs within the AC resistance the calculated one skin depth and is uniformly distributed over the calculated one skin depth at the first frequency, and is multiplied by a factor of greater than or equal to one to account for resistive losses in a return plane. 
     
     
       15. A method for fabricating on interconnect path as recited in claim 8 wherein the known resistive value per unit length of the selected material comprises an effective DC resistance and an effective AC resistance, assumption that all conduction occurs within the AC resistance the calculated one skin depth and is uniformly distributed over the calculated one skin depth at the second frequency, and is multiplied by a factor of greater than or equal to one to account for resistive losses in a return plane. 
     
     
       16. A method for fabricating on interconnect path as recited in claim 9 wherein the known resistive value per unit length of the selected material comprises an effective DC resistance and an effective AC resistance, assumption that all conduction occurs within the AC resistance the calculated one skin depth and is uniformly distributed over the calculated one skin depth at the third frequency, and is multiplied by a factor of greater than or equal to one to account for resistive losses in a return plane.