Internal clock signal generation circuit including delay line, and synchronous type semiconductor memory device including internal clock signal

Abstract

An internal clock generation circuit includes a delay line in which a plurality of inverter circuits are connected in series. A switch and a capacitor are connected to an output node of each inverter circuit. The switch connected to each inverter circuit is turned on/off individually according to respective control signals. In response to the switch being turned on, the output node of a corresponding inverter circuit and the capacitor are connected, whereby the capacitance of the output node of the corresponding inverter circuit is altered. As a result, the transmission rate of the signal is altered.

What is claimed is: 
     
       1. An internal clock signal generation circuit for generating an internal clock signal synchronizing in phase with an external clock signal, comprising: a delay line for delaying said external clock signal and providing said internal clock signal, said delay line including a plural number of delay elements connected in series;   a phase detection circuit for detecting a phase difference between said external clock signal and said internal clock signal to determine a delay time required to delay said external clock signal; and   a delay control circuit, including a plural number of capacitance circuits coupled to outputs of the plural number of said delay elements in parallel, each of said plural number of capacitance circuits controlling a delay of a corresponding delay element in response to a detected result of said phase detection circuit.   
     
     
       2. The internal clock signal generation circuit according to claim 1, said plural number of capacitance circuits of said delay control circuit including: a plurality of first capacitor elements provided corresponding to respective output nodes of said plural number of delay elements, and   a plurality of first switches connected between said plurality of first capacitor elements and said output nodes, respectively,   each said first switch establishing a connected state/non-connected state between a corresponding said first capacitor element and a corresponding said output node individually by switching between an on state and an off state according to a detected result of the phase difference of said phase detection circuit.     
     
     
       3. The internal clock signal generation circuit according to claim 1, said plural number of capacitance circuits of said delay control circuit including: a plurality of second capacitor elements provided corresponding to respective output nodes of said plural number of delay elements,   a plurality of third capacitor elements provided corresponding to respective output nodes of said plural number of delay elements, each having a capacitance greater than the capacitance of each of said plurality of second capacitor elements,   a plurality of second switches each for establishing a connected state/non-connected state between a corresponding said second capacitor element and a corresponding said output node by switching between an on state and an off state according to a detected result of the phase difference of said phase detection circuit, and   a plurality of third switches each for establishing a connected state/non-connected state between a corresponding said third capacitor element and a corresponding said output node by switching between an on state and an off state according to a detected result of the phase difference of said phase detection circuit,     said plurality of second switches being selectively turned on when the delay time required to delay said external clock signal is relatively short, and said plurality of second switches being turned on and said plurality of third switches being selectively turned on when the delay time required to delay said external clock signal is relatively long.   
     
     
       4. The internal clock signal generation circuit according to claim 1, said plural number of capacitance circuits of said delay control circuit including: a plurality of fourth capacitor elements provided corresponding to respective output nodes of said plural number of delay elements, and   a plurality of current adjust circuits, connected between said plurality of fourth capacitor elements and said output nodes, respectively,   each said current adjust circuit adjusting a value of a current flowing from a corresponding said output node to a corresponding said fourth capacitor element according to a detected result of the phase difference of said phase detection circuit.     
     
     
       5. The internal clock signal generation circuit according to claim 1, said plural number of capacitance circuits of said delay control circuit including a plurality of apparent capacitor elements provided corresponding to respective output nodes of said plural number of delay elements,   said plurality of apparent capacitor elements each generating an apparent capacitance on a corresponding output node under control of said phase control circuit.   
     
     
       6. The internal clock signal generation circuit according to claim 1, said phase detection circuit including: a first delay circuit for delaying said external clock signal,   a second delay circuit for delaying said internal clock signal, and   a comparator for comparing a phase difference between an output of said first delay circuit and an output of said second delay circuit,   sensitivity of said phase comparator being degraded by increasing the delay time of said first delay circuit and the delay time of the second delay circuit when the delay time required to delay said external clock signal is relatively long.     
     
     
       7. An internal clock signal generation circuit for generating an internal clock signal synchronizing in phase and in frequency with said an external clock signal, comprising: an oscillation circuit including a delay line determining an oscillating frequency of said internal clock signal, said delay line including a plural number of delay elements connected in series;   a phase detection circuit for detecting a phase difference between said external clock signal and said internal clock signal output from said oscillation circuit to determine a delay time required to delay said external clock signal; and   a delay control circuit including a plural number of capacitance circuits coupled to outputs of the plural number of said delay elements in parallel each of said plural number of capacitance circuits controlling a delay of a corresponding delay element in response to a detected result of said phase detection circuit.   
     
     
       8. The internal clock signal generation circuit according to claim 7, said plural number of capacitance circuits of said delay control circuit including: a plurality of first capacitor elements provided corresponding to respective output nodes of said plural number of delay elements, and   a plurality of first switches connected between said plurality of first capacitor elements and said output nodes, respectively,   each said first switch establishing a connected state/non-connected state between a corresponding said first capacitor element and a corresponding said output node individually by switching between an on state and an off state according to a detected result of the phase difference from said phase detection circuit.     
     
     
       9. The internal clock signal generation circuit according to claim 7, said plural number of capacitance circuits of said delay control circuit including: a plurality of second capacitor elements provided corresponding to respective output nodes of said plural number of delay elements,   a plurality of third capacitor elements provided corresponding to respective output nodes of said plural number of delay elements, each having a capacitance greater than the capacitance of each of said plurality of second capacitor elements,   a plurality of second switches each for establishing a connected state/non-connected state between a corresponding said second capacitor elements and a corresponding said output node by switching between an on state and an off state according to a detected result of the phase difference from said phase detection circuit,   a plurality of third switches each for establishing a connected state/non-connected state between a corresponding said plurality of third capacitor elements and a corresponding said output node by switching between an on state and an off state according to a detected result of the phase difference of said phase detection circuit,   said plurality of second switches being selectively turned on when the delay time required to delay said external clock signal is relatively short, and said plurality of second switches being turned on and said plurality of third switches being selectively turned on when the delay time required to delay said external clock signal is relatively long.     
     
     
       10. The internal clock signal generation circuit according to claim 7, wherein said plural number of capacitance circuits of said delay control circuit including a plurality of fourth capacitor elements provided corresponding to respective output nodes of said plural number of delay elements, and   a plurality of current adjust circuits connected between said plurality of fourth capacitor elements and said output nodes, respectively,   each said current adjust circuit adjusting value of a current flowing from a corresponding said output node to a corresponding said fourth capacitor element according to a detected result of the phase difference of said phase detection circuit.     
     
     
       11. The internal clock signal generation circuit according to claim 7, said plural number of capacitance circuits of said delay control circuit including a plurality of apparent capacitor elements provided corresponding to respective output nodes of said plural number of delay elements,   said plurality of apparent capacitor elements each generating an apparent capacitance on a corresponding output node under control of said phase control circuit.   
     
     
       12. The internal clock signal generation circuit according to claim 7, said phase detection circuit including a first delay circuit for delaying said external clock signal,   a second delay circuit for delaying said internal clock signal, and   a comparator for comparing a phase difference between an output of said first delay circuit and an output of said second delay circuit,   sensitivity of said phase comparator being degraded by increasing the delay time of said first delay circuit and the delay time of said second delay circuit when the delay time required to delay said external clock signal is long.     
     
     
       13. A synchronous semiconductor memory device for entering an external signal including a control signal, an address signal, and an input signal in synchronization with an external clock signal, comprising: a memory array including a plurality of memory cells arranged in a matrix in row and column directions;   internal clock generation circuit for providing an internal clock signal synchronizing in phase with said external clock signal; and   data input/output circuit for selecting said memory cell to carry out data writing and reading with respect to said selected memory cell in synchronization with said internal clock signal,   said internal clock signal generation circuit including: a delay line for delaying said external clock signal and providing said internal clock signal, said delay line including a plural number of delay elements connected in series,   a phase detection circuit for detecting a phase difference between said external clock signal and said internal clock signal to determine a delay time required to delay said external clock signal, and   a delay control circuit including a plural number of capacitance circuits coupled to outputs of the plural number of said delay elements in parallel, each of said plural number of capacitance circuits controlling a delay of a corresponding delay element in response to a detected result of said phase detection circuit.     
     
     
       14. The synchronous type semiconductor memory device according to claim 13, said plural number of capacitance circuits of said delay control circuit including: a plurality of first capacitor elements, provided corresponding to respective output nodes of said plural number of delay elements,   a plurality of first switches connected between said plurality of first capacitor elements and said output nodes, respectively,   each said first switch establishing a connected state/non-connected state between a corresponding said first capacitor element and a corresponding said output node individually by switching between an on state and an off state according to a detected result of the phase difference from said phase detection circuit.