Chip size package and method of manufacturing the same

Abstract

A chip size package is constituted by a chip on which an integrated circuit is formed, and plated bumps are formed at terminal portions of the integrated circuit, a flexible two-layered printed-circuit board having interlevel conductive bumps for electrically connecting metal patterns formed on the two surfaces of the flexible board, and an anisotropic conductive film for electrically connecting the plated bumps arranged on the chip to the flexible two-layered printed-circuit board, and fixing the chip onto the flexible two-layered printed-circuit board. With these features, the chip size package is excellent in mass production without any sealing by potting and any setting/removing on/from a convey jig and the like for every product.

I claim: 
     
       1. A chip size package, comprising: an IC chip on which a conductive bump is formed at a terminal portion of said IC chip;   a printed-circuit board having an interlevel conductive bump for electrically connecting conductive patterns formed on two surfaces via an insulating layer; and   an anisotropic conductive film in the form of a sheet prepared by dispersing conductive particles in a thermosetting resin for electrically connecting said conductive bump formed on said IC chip to said conductive pattern arranged on said printed-circuit board, for bonding said IC chip to said printed-circuit board, and for sealing a bonded portion between said IC chip and said printed-circuit board.   
     
     
       2. A package according to claim 1, characterized in that said printed-circuit board is a flexible printed-circuit board. 
     
     
       3. A package according to claim 1 or 2, characterized in that said interlevel conductive bump arranged on said printed-circuit board is laid out at a position corresponding to a position where said conductive bump of said IC chip is laid out with respect to a bonding surface between said IC chip and said printed-circuit board. 
     
     
       4. A package according to claim 1 or 2, characterized in that said interlevel conductive bump formed on said printed-circuit board is laid out at a position which does not correspond to a position where said conductive bump of said IC chip is laid out with respect to a bonding surface between said IC chip and said printed-circuit board. 
     
     
       5. A package according to claim 1 or 2, characterized in that said interlevel conductive bump arranged on said printed-circuit board is laid out at a position corresponding to a position where said conductive bump of said IC chip is laid out with respect to a bonding surface between said IC chip and said printed-circuit board. 
     
     
       6. A package according to claim 1 or 2, characterized in that said interlevel conductive bump formed on said printed-circuit board is laid out at a position which does not correspond to a position where said conductive bump of said IC chip is laid out with respect to a bonding surface between said IC chip and said printed-circuit board.