Dram with dummy word lines

Abstract

A plurality of word lines are disposed on the surface of a semiconductor substrate in a first direction. Two dummy word lines are disposed outside of the outermost word line among the word lines. MISFETs are disposed in correspondence with the word lines and dummy word lines. MISFETs are regularly disposed in the first direction and in a second direction crossing the first direction. One storage region among the source and drain regions of each MISFET is formed with a storage contact hole. The storage regions are distributed only in an area inside of the outermost dummy word line among the dummy word lines. A capacitor is connected to the storage region at the bottom of each storage contact hole. Different voltages are applied to the dummy word lines and the bit regions disposed outside of the outermost dummy word line. A semiconductor device capable of suppressing a standby current error is provided.

What is claimed is: 
     
       1. A semiconductor device comprising: a semiconductor substrate;   a plurality of word lines disposed at an interval on a surface of the semiconductor substrate and extending in a first direction;   at least two dummy word lines disposed at a space and extending in the first direction, the dummy word lines being disposed in an area outside of an outermost word line of the plurality of word lines;   a plurality of MISFETs formed in correspondence with each of the word lines and the dummy word lines and regularly disposed in the first direction and in a second direction crossing the first direction, the word line or dummy word line of each MISFET serving also as a corresponding gate electrode of each MISFET;   an interlayer insulating film covering the MISFETs;   storage contact holes formed through the interlayer insulating film, each being disposed in one storage region among source and drain regions of each MISFET, the storage regions being distributed only in an area inside of an outermost dummy word line among the dummy word lines;   a capacitor formed on a bottom of each storage contact hole in each of the storage regions;   a word driver circuit connected to the word lines for selectively applying an electrical signal to each of the word lines;   a first voltage application circuit for applying a first fixed voltage to the dummy word lines; and   a second voltage application circuit for applying a second fixed voltage different from the first fixed voltage to each bit region, disposed outside of the outermost dummy word line, among the source and drain regions of each MISFET corresponding to the outermost dummy word line.   
     
     
       2. A semiconductor device according to claim 1, further comprising an outermost impurity diffusion region disposed outside of the outermost dummy word line in a direction along the dummy word line and formed by doping impurities in a surface layer of the semiconductor substrate, the outermost impurity diffusion region serving as bit regions of a plurality of MISFETs corresponding to the outermost dummy word line. 
     
     
       3. A semiconductor device according to claim 1, wherein the storage regions of the MISFETs corresponding to each of the two dummy word lines are disposed between the two dummy word lines and are made in a d.c. floating state. 
     
     
       4. A semiconductor device according to claim 3, wherein the storage regions of the MISFETs corresponding to each of the two dummy word lines are connected together by an impurity diffusion region in a floating state formed in a surface layer of the semiconductor substrate. 
     
     
       5. A semiconductor device according to claim 1, wherein each of the storage contact holes formed in correspondence with the storage regions of the MISFETs corresponding to each of the two dummy word lines partially overlaps at least one of the two dummy word lines as viewed along a direction normal to the semiconductor substrate. 
     
     
       6. A semiconductor device according to claim 1, further comprising a plurality of bit lines formed on the surface of the semiconductor substrate and extending in the second direction, the bit lines being disposed in correspondence with the MISFETs disposed in the first direction and connected to bit regions of the corresponding MISFETs. 
     
     
       7. A semiconductor device according to claim 6, further comprising a sense amplifier circuit connected to the bit lines for detecting a voltage on each bit line, the sense amplifier circuit being disposed outside of the bit regions corresponding to the outermost dummy word line. 
     
     
       8. A semiconductor device according to claim 7, wherein an outermost bit line among the bit lines is not connected to the sense amplifier circuit. 
     
     
       9. A semiconductor device according to claim 1, further comprising an etching stopper film formed under the interlayer insulating film, the etching stopper film covering surfaces of the dummy word lines and made of material having a different etching resistance from material of the interlayer insulating film.