ATM cell sending system

Abstract

An ATM cell sending system includes a first memory, a second memory, a retrieval circuit, and a memory control circuit. The first memory temporarily stores an input cell, outputs a cell storage address, and, in response to input of the cell storage address, outputs the cell stored at the input cell storage address. The second memory stores the cell storage address from the first memory and outputs the readout cell storage address to the first memory. The retrieval circuit uses an address corresponding to a reservation time for cell sending as a start address to retrieve a first free address after the reservation time from the second memory. The memory control circuit writes the cell storage address of the first memory at the free address of the second memory, which is retrieved by the retrieval circuit, and reads out the cell storage address of the first memory from an address of the second memory which corresponds to a current time.

What is claimed is: 
     
       1. An asynchronous transfer mode (ATM) cell sending system comprising: a first memory for temporarily storing an input cell at a cell storage address of said first memory and outputting said cell storage address;   a second memory for storing said cell storage address of said first memory at an address of said second memory and outputting said cell storage address from said address of said second memory to the input of said first memory wherein said first memory reads out the cell stored at said cell storage address in response to the input of said cell storage address;   retrieval means for retrieving from said second memory a first free address of said second memory after an address corresponding to an ideal cell sending time for said input cell; and   memory control means for writing said cell storage address of said first memory at said free address of said second memory, wherein said free address is retrieved by said retrieval means, and reading out a cell storage address of said first memory from an address of said second memory which corresponds to a current time.   
     
     
       2. The system according to claim 1, further comprising: cell sending time determination means for determining an ideal cell sending time as the reservation time for cell sending in response to input of the cell; and   conversion means for converting the ideal cell sending time from said cell sending time determination means into a corresponding address of said second memory, and   wherein said retrieval means retrieves the free address of said second memory after the ideal cell sending time by using the address from said conversion means as the start address.   
     
     
       3. The system according to claim 1, wherein said memory control means writes at an address of said second memory a reservable pattern to denote a free address of said second memory, and said retrieval means retrieves the free address of said second memory on the basis of the reservable pattern. 
     
     
       4. The system according to claim 1, wherein respective addresses of said second memory correspond with ascending cell sending times. 
     
     
       5. The system according to claim 1, wherein said second memory comprises a contents addressable memory (CAM) capable of designating a retrieval start address. 
     
     
       6. The system according to claim 5, wherein said retrieval means comprises a retrieval circuit for retrieving all free addresses of said CAM, an extraction circuit for extracting, from the free addresses retrieved by said retrieval circuit, free addresses after the retrieval start address, and a selection circuit for selecting a free address closest to the retrieval start address from the free addresses extracted by said extraction circuit. 
     
     
       7. The system according to claim 1, wherein said first memory has a management circuit for managing free addresses of said first memory, storing an input cell at one of the free addresses, and outputting the address at which said input cell is stored to said second memory.