Class D amplifier with scaled clock and related methods

Abstract

A class D amplifier includes a scaled clock generator for generating a scaled clock signal based upon an N bit pulse code modulation (PCM) signal and a K most significant bits (MSBs) PCM signal from the N bit PCM signal; and a PCM to pulse width modulation (PWM) converter for converting the K MSBs signal to a PWM output signal based upon the scaled clock signal. The amplifier preferably includes an input circuit for generating the N bit PCM signal from an input signal, and a truncation circuit for truncating the N bit PCM digital signal to the K MSBs PCM signal. The PWM output signal may be coupled to a switch driver which, in turn, is coupled to one or more output switches. The amplifier uses a practically implemented reference clock without the drawbacks associated with a conventional noise shaping filter. The scaled clock generator may be provided by a divider having a first input receiving the N bit digital input signal and a second input receiving the K MSBs signal for generating a clock scale ratio signal. The scaled clock generator may also include a reference clock, and a numerically controlled clock connected thereto for producing the scaled clock signal. The scaled clock generator may further include a bias circuit for inputting a bias value to the divider so that a numerator thereof is greater than zero.

That which is claimed is: 
     
       1. A class D amplifier comprising: input means for generating an N bit Pulse Code Modulated (PCM) signal from an input signal;   truncation means for truncating the N bit PCM digital signal to a K most significant bits (MSBs) PCM signal;   scaled clock generating means for generating a scaled clock signal based upon the N bit PCM signal and the K MSBs PCM signal;   a pulse code modulation (PCM) to pulse width modulation (PWM) converter for converting the K MSBs signal to a PWM output signal based upon the scaled clock signal.   
     
     
       2. A class D amplifier according to claim 1 wherein said scaled clock generating means comprises a divider having a first input receiving the N bit digital input signal and a second input receiving the K MSBs signal for generating a clock scale ratio signal. 
     
     
       3. A class D amplifier according to claim 2 wherein the first input of said divider is a denominator input and the second input of said divider is a numerator input. 
     
     
       4. A class D amplifier according to claim 2 wherein said scaled clock generating means further comprises: a reference clock; and   a numerically controlled clock having a first input connected to said reference clock and a second input connected to receive the clock scale ratio signal for producing the scaled clock signal.   
     
     
       5. A class D amplifier according to claim 2 further comprising bias means for inputting a bias value to said divider so that a numerator thereof is greater than zero. 
     
     
       6. A class D amplifier according to claim 5 further bias subtracting means for subtracting the bias downstream from said PCM to PWM converter. 
     
     
       7. A class D amplifier according to claim 1 wherein said PCM to PWM converter comprises one of a leading edge, trailing edge, and symmetric PCM to PWM converter. 
     
     
       8. A class D amplifier according to claim 1 wherein said PCM to PWM converter comprises one of a binary or trinary polarity PCM to PWM converter. 
     
     
       9. A class D amplifier according to claim 1 further comprising a switch driver connected to the PWM output signal of said PCM to PWM converter. 
     
     
       10. A class D amplifier according to claim 9 further comprising at least one power switch connected to said switch driver. 
     
     
       11. A class D amplifier comprising: input means for generating an N bit Pulse Code Modulated (PCM) signal from an input signal;   truncation means for truncating the N bit PCM signal to a K most significant bits (MSBs) PCM signal;   a divider having a first input receiving the N bit input signal and a second input receiving the K MSBs signal for generating a clock scale ratio signal;   a reference clock;   a numerically controlled clock having a first input connected to said reference clock and a second input connected to receive the clock scale ratio signal for producing a scaled clock signal therefrom; and   a pulse code modulation (PCM) to pulse width modulation (PWM) converter for converting the K MSBs signal to a PWM output signal based upon the scaled clock signal.   
     
     
       12. A class D amplifier according to claim 11 wherein the first input of said divider is a denominator input and the second input of said divider is a numerator input. 
     
     
       13. A class D amplifier according to claim 11 further comprising bias means for inputting a bias value to said divider so that a numerator thereof is greater than zero. 
     
     
       14. A class D amplifier according to claim 13 further bias subtracting means for subtracting the bias downstream from said PCM to PWM converter. 
     
     
       15. A class D amplifier according to claim 11 wherein said PCM to PWM converter comprises one of a leading edge, trailing edge, and symmetric PCM to PWM converter. 
     
     
       16. A class D amplifier according to claim 11 wherein said PCM to PWM converter comprises one of a binary or trinary polarity PCM to PWM converter. 
     
     
       17. A class D amplifier according to claim 11 further comprising a switch driver connected to the PWM output signal of said PCM to PWM converter. 
     
     
       18. A class D amplifier according to claim 17 further comprising at least one power switch connected to said switch driver. 
     
     
       19. A class D amplifier comprising: a scaled clock generator for generating a scaled clock signal based upon an N bit pulse code modulation (PCM) signal and a K most significant bits (MSBs) PCM signal from the N bit PCM signal;   a PCM to pulse width modulation (PWM) converter for converting the K MSBs signal to a PWM output signal based upon the scaled clock signal; and   a switch driver connected to the PWM output signal of said PCM to PWM converter.   
     
     
       20. A class D amplifier according to claim 19 wherein said scaled clock generating means comprises a divider having a first input receiving the N bit digital input signal and a second input receiving the K MSBs signal for generating a clock scale ratio signal. 
     
     
       21. A class D amplifier according to claim 20 wherein the first input of said divider is a denominator input and the second input of said divider is a numerator input. 
     
     
       22. A class D amplifier according to claim 20 wherein said scaled clock generating means further comprises: a reference clock; and   a numerically controlled clock having a first input connected to said reference clock and a second input connected to receive the clock scale ratio signal for producing the scaled clock signal.   
     
     
       23. A class D amplifier according to claim 20 further comprising bias means for inputting a bias value to said divider so that a numerator thereof is greater than zero. 
     
     
       24. A class D amplifier according to claim 23 further bias subtracting means for subtracting the bias downstream from said PCM to PWM converter. 
     
     
       25. A class D amplifier according to claim 19 wherein said PCM to PWM converter comprises one of a leading edge, trailing edge, and symmetric PCM to PWM converter. 
     
     
       26. A class D amplifier according to claim 19 wherein said PCM to PWM converter comprises one of a binary or trinary polarity PCM to PWM converter. 
     
     
       27. A class D amplifier according to claim 19 further comprising at least one power switch connected to said switch driver. 
     
     
       28. A method of performing class D amplification comprising the steps of: generating a scaled clock signal based upon an N bit pulse code modulation (PCM) signal and a K most significant bits (MSBs) PCM signal from the N bit PCM signal, the step of generating the scaled clock signal comprising dividing the K MSBs signal by the N bit digital input signal for generating a clock scale ratio signal; and   converting the K MSBs signal to a pulse width modulation (PWM) output signal based upon the scaled clock signal.   
     
     
       29. A method according to claim 28 wherein the step of generating the scaled clock signal further comprises the step of controlling a numerically controlled clock by the clock scale ratio signal for producing the scaled clock signal. 
     
     
       30. A method according to claim 28 further comprising the step of inputting a bias value for the dividing step so that a numerator is greater than zero. 
     
     
       31. A method according to claim 30 further comprising the step of subtracting the bias downstream from the PCM to PWM converting. 
     
     
       32. A method according to claim 28 wherein the step of converting comprises converting by one of leading edge, trailing edge, and symmetric PCM to PWM converting. 
     
     
       33. A method according to claim 28 wherein the step of converting comprises converting by one of a binary or trinary polarity PCM to PWM converting. 
     
     
       34. A method according to claim 28 further comprising the step of operating at least one power switch based upon the PWM output signal.