System and method for accessing data between a host bus and system memory buses in which each system memory bus has a data path which is twice the width of the data path for the host bus

Abstract

A microcomputer system memory architecture and method allows the system memory to provide data access at high speeds in a burst mode. The architecture and method utilizes a system memory controller capable of performing the addressing of the system memory. The microprocessor and the system memory communicate via a high speed host bus. The system memory is comprised of multiple 64-bit system memory buses to permit high speed data transfer to the microprocessor in a burst mode without the need for an external cache.

What is claimed is: 
     
       1. A system for high speed data access in a microcomputer computer, comprising: a host bus having a data path which is a first number of bits wide;   a system memory, coupled to the host bus, the system memory including at least two system memory buses within the system memory, each system memory bus having two sections, a data path of each section being the first number of bits wide, data within the system memory being retrieved and stored through the at least two system memory buses, and   latching means within the system memory, coupled between the host bus and the system memory buses, for latching data between the host bus and the system memory buses so that for a single data access on one of the system memory buses, two data accesses are made on the host bus;     a system processor, coupled to the host bus, the host bus providing a communication link between the system processor and the system memory.   
     
     
       2. A system according to claim 1, wherein the latching means for each system memory bus comprises two bidirectional latching transceivers situated to read from system memory in parallel and situated to transmit system memory data to the host bus. 
     
     
       3. A system according to claim 2, wherein said system memory is controlled by a system memory controller. 
     
     
       4. A system according to claim 3, wherein said system memory controller is driven at a clock speed of at least 25 Megahertz. 
     
     
       5. A system according to claim 1, wherein the system memory additionally comprises SIMMs coupled to the system memory buses. 
     
     
       6. A system according to claim 5, wherein said system memory comprises page mode DRAMs situated on said SIMMs. 
     
     
       7. A system according to claim 3, wherein the system memory additionally comprises static column DRAMs situated on said SIMMS. 
     
     
       8. A system according to claim 1, wherein said host bus operates synchronously with said microprocessor. 
     
     
       9. A system according to claim 1, wherein said microprocessor is driven at a clock speed of at least 25 Megahertz. 
     
     
       10. A system according to claim 1, wherein said system memory buses operate synchronously with said host bus. 
     
     
       11. A system according to claim 1, wherein said host bus can access data in said system memory with a bandwidth of 50 megabytes per second while operating in a burst mode. 
     
     
       12. A system as in claim 1 wherein the first number is 32. 
     
     
       13. A method of data retrieval from a system memory having at least two parallel system memory buses, each of the two parallel system memory buses being located within the system memory and being coupled by a latch to a host bus, data within the system memory being retrieved and stored through the at least two system memory buses, the host bus providing a communication link between the system memory and a system processor, a data path for each of the system memory buses being twice as wide as a data path for the host bus, the method comprising the following steps: (a) selecting one of the system memory buses;   (b) retrieving data bits across the entire data path of the system memory bus selected in step (a),   (c) electrically transmitting a first half of the data bits retrieved in step (b) onto said host bus, and   (d) electrically transmitting a second half of the data bits retrieved in step (b) onto said host bus.   
     
     
       14. A method as in claim 13 wherein the data path for each of the system memory buses is 64 bits wide and the data path for the host bus is 32 bits wide. 
     
     
       15. A method of transferring data bits from a system memory bus onto a host bus in a microcomputer having a system memory with at least two parallel system memory buses, each of the two parallel system memory buses being located within the system memory and a data path for each of the system memory buses being twice as wide as a data path for the host bus, data within the system memory being retrieved and stored through the at least two system memory buses, the host bus providing a communication link between the system memory and a system processor, the method comprising the following steps: (a) providing two latching transceivers for each system memory bus, for each system memory bus, each of the two latching transceivers being coupled to the host bus and being adapted to access data bits for half the data path of the system memory bus,   (b) upon a transfer of data between a first of the system memory buses and the host bus, alternately activating the two latching transceivers for the first system memory bus to thereby perform data transfers of data between the first system memory bus and the host bus.   
     
     
       16. A method as in claim 15 wherein the data path for each of the system memory buses is 64 bits wide and the data path for the host bus is 32 bits wide. 
     
     
       17. A method as in claim 15 wherein the data path for the system memory bus is 64 bits wide and the data path for the host bus is 32 bits wide. 
     
     
       18. A method of transferring data bits from a system memory bus onto a host bus in a microcomputer system memory, the system memory bus being coupled to the host bus via two parallel latching transceivers and a data path of the system memory bus being twice as wide as a data path for the host bus, data within the system memory being retrieved and stored through the at least two system memory buses, the host bus providing a communication link between the system memory and a system processor, the method comprising the following steps: (a) reading a first set of data bits from said system memory bus into said two parallel latching transceivers,   (b) activating a first latching transceiver to thereby transfer a first half of the data bits read in step (a) onto said host bus,   (c) activating a second latching transceiver to thereby transfer a second half of the data bits read in step (a) onto said host bus,   (d) reading a second set of data bits from said memory bus into said two parallel latching transceivers,   (e) activating said first latching transceiver to thereby transfer a first half of the data bits read in step (d) onto said host bus,   (f) activating said second latching transceiver to thereby transfer a second half of the data bits read in step (d) onto said host bus.