Silicon on insulator substrate with improved insulation patterns

Abstract

The present invention provides a silicon-on-insulator substrate comprising a first silicon substrate, a second silicon substrate bonded to the first silicon substrate, a plurality of insulation film patterns formed on a plurality of first type regions of an interface between the first and second silicon substrate, so that the first and second silicon substrates on the plurality of first type regions are indirectly bonded through the plurality of insulation film patterns while the first and second silicon substrates on a plurality of second type regions are directly bonded to each other, wherein each of the plurality of first type regions is bounded on all sides by the plurality of second type regions while each of the plurality of second type regions is bounded on all sides by the plurality of first type regions.

What is claimed is: 
     
       1. A silicon-on-insulator substrate comprising a first silicon substrate, a second silicon substrate bonded to said first silicon substrate, a plurality of insulation film patterns formed on a plurality of first type regions of an interface between said first and second silicon substrates, so that said first and second silicon substrates on said plurality of first type regions are indirectly bonded through said plurality of insulation film patterns whilst said first and second silicon substrates on a plurality of second type regions are directly bonded to each other, wherein each of said plurality of first type regions is bounded on all sides by said plurality of second type regions whilst each of said plurality of second type regions is bounded on all sides by said plurality of first type regions.   
     
     
       2. The silicon-on-insulator substrate as claimed in claim 1, wherein said plurality of insulation film patterns provided on said plurality of first type regions are in the shape of checkered patterns. 
     
     
       3. The silicon-on-insulator substrate as claimed in claim 2, wherein at least one pair of said first and second type regions is included in each chip which is to be cut therefrom. 
     
     
       4. The silicon-on-insulator substrate as claimed in claim 3, wherein two pairs of said first and second type regions are included in each said chip. 
     
     
       5. The silicon-on-insulator substrate as claimed in claim 1, wherein said plurality of insulation film patterns provided on said plurality of first type regions are periodical patterns having a periodicity based upon a size of chips which are aligned in matrix in laminations of said first and second substrates and are to be cut therefrom. 
     
     
       6. The silicon-on-insulator substrate as claimed in claim 5, wherein at least one of said first type regions and at least one of said second type regions are included in each of the chips, and wherein said at least one of said second type regions is surrounded by said at least one of said first type regions in said chips. 
     
     
       7. The silicon-on-insulator substrate as claimed in claim 1, wherein said first and second type regions are alternately and periodically arranged in both first and second directions which are perpendicular to each other but parallel to said interface. 
     
     
       8. The silicon-on-insulator substrate as claimed in claim 1, wherein said first and second type regions have the same size and the same geometrical shape. 
     
     
       9. The silicon-on-insulator substrate as claimed in claim 1, wherein control circuits are formed in the first type regions whilst vertical power MOS transistors are formed in the second type regions. 
     
     
       10. A silicon-on-insulator substrate comprising a first silicon substrate, a second silicon substrate bonded to said first silicon substrate, a plurality of insulation film patterns formed on a plurality of first type regions of an interface between said first and second silicon substrates, so that said first and second silicon substrates on said plurality of first type regions are indirectly bonded through said plurality of insulation film patterns whilst said first and second silicon substrates on a plurality of second type regions are directly bonded to each other, wherein each of said plurality of second type regions is bounded on all sides by a respective one of said plurality of first type regions.   
     
     
       11. The silicon-on-insulator substrate as claimed in claim 10, wherein at least one pair of said first and second type regions is included in each chip which is to be cut therefrom. 
     
     
       12. The silicon-on-insulator substrate as claimed in claim 10, wherein said first type regions are square and said second type regions are rectangles that are each completely enclosed within a respective one of said squares. 
     
     
       13. The silicon-on-insulator as claimed in claim 10, wherein control circuits are formed in the first type regions whilst vertical power MOS transistors are formed in the second type regions. 
     
     
       14. A silicon-on-insulator substrate comprising a first silicon substrate, a second silicon substrate bonded to said first silicon substrate, a plurality of insulation film patterns formed on a plurality of first type regions of an interface between said first and second silicon substrates, so that said first and second silicon substrates on said plurality of first type regions are indirectly bonded through said plurality of insulation film patterns whilst said first and second silicon substrates on a plurality of second type regions are directly bonded to each other, wherein said first and second type regions are alternately and periodically arranged in both first and second directions which are perpendicular to each other and parallel to said interface, and   wherein two pairs of said first and second type regions are included in each chip cut from said substrate.   
     
     
       15. The silicon-on-insulator substrate as claimed in claim 14, wherein plurality of insulation film patterns provided on said plurality of first type regions are in the shape of checkered patterns. 
     
     
       16. The silicon-on-insulator substrate as claimed in claim 14, wherein said plurality of insulation film patterns provided on said plurality of first type regions are periodical patterns having a periodicity based upon a size of the chip. 
     
     
       17. The silicon-on-insulator substrate as claimed in claim 16, wherein said at least one of said second type regions is surrounded by said at least one of said first type regions in said chip. 
     
     
       18. The silicon-on-insulator substrate as claimed in claim 14, wherein said first and second type regions have the same size and the same geometrical shape. 
     
     
       19. The silicon-on-insulator substrate as claimed in claim 14, wherein control circuits are formed in the first type regions whilst vertical power MOS transistors are formed in the second type regions.