Imbedded PCB AC coupling capacitors for high data rate signal transfer

Abstract

A method and apparatus for coupling high speed data components using imbedded PCB AC coupling capacitors is disclosed. The capacitor comprises a first and a second conductive plate of polygonal shape coupled to surrounding circuitry at the polygonal vertices of the polygonal plates. This configuration results in improved capacitor performance, particularly with respect to capacitive impedance and reflected waves for high bandwidth signals at the frequency ranges of interest.

What is claimed is: 
     
       1. A capacitor, comprising: a substantially insulative printed circuit board first layer having a first side and a second side;   a first substantially conductive surface disposed on the first side of the substantially insulative printed circuit board first layer;   a second substantially conductive surface substantially oppositionally disposed from the first substantially conductive surface on the second side of the substantially insulative printed circuit board first layer; and   wherein the first and second conductive surfaces arc substantially polygonal in shape.   
     
     
       2. The capacitor of claim 1, further comprising a first substantially conductive path coupled to the first substantially conductive surface at a vertex of the first substantially conductive surface and a second substantially conductive path coupled to a vertex of the second substantially conductive surface. 
     
     
       3. The capacitor of claim 1, wherein the substantially polygonal conductive surface is trapezoidally-shaped. 
     
     
       4. The capacitor of claim 1, wherein the substantially polygonal conductive surfaces are diamond-shaped. 
     
     
       5. The capacitor of claim 1, wherein the substantially polygonal conductive surfaces are square-shaped. 
     
     
       6. The capacitor of claim 1, wherein the substantially polygonal conductive surfaces are formed of copper. 
     
     
       7. The capacitor of claim 1, wherein the trapezoidal shape of the first and second conductive surfaces are substantially symmetric about a trapezoid axis. 
     
     
       8. The capacitor of claim 1, further comprising: a substantially insulative printed circuit board second layer having a first aperture therethrough, and a substantially insulative printed circuit board third layer having a second aperture therethrough, wherein first layer is disposed between the second layer and the third layer;   a first conductive path electrically coupled to the first conductive surface via the first aperture; and   a second conductive path electrically coupled to the first conductive surface via the second aperture.   
     
     
       9. The capacitor of claim 8, wherein the first conductive path is an electrical trace on a surface of the second layer, and the second conductive path is an electrical trace on a surface of the third layer. 
     
     
       10. The capacitor of claim 1, further comprising: a substantially insulative printed circuit board second layer;   a substantially insulative printed circuit board third layer;   a substantially insulative printed circuit board fourth layer;   a substantially insulative printed circuit board fifth layer;   a third conductive surface disposed between the fourth layer and the second layer and electrically coupled to the second conductive surface;   a fourth conductive surface disposed between the third layer and the fifth layer and electrically coupled to the first conductive surface;   wherein the third and fourth conductive surfaces are substantially polygonal in shape and are aligningly disposed in relation to the third and the first and the second conductive surfaces;   a first conductive path electrically coupled to the third and the second conductive surfaces; and   a second conductive path electrically coupled to the first and the fourth conductive surfaces.   
     
     
       11. The capacitor of claim 10, wherein the third conductive surface, the third conductive surface, the second conductive surface, and the first conductive path are electrically coupled by a first via through the substantially insulative printed circuit board first, second, third, fourth, and fifth layers, and the first conductive surface, the fourth conductive surface and the second conductive path are electrically coupled by a first via through the substantially insulative printed circuit board first, second, third, fourth, and fifth layers. 
     
     
       12. The capacitor of claim 11, wherein the third conductive surface is disposed on the second layer. 
     
     
       13. The capacitor of claim 11, wherein the third conductive surface is disposed on the fourth layer. 
     
     
       14. The capacitor of claim 1, wherein the substantially insulative material has a dielectric constant of between approximately 4.0 and 4.5. 
     
     
       15. A capacitor, comprising: a substantially insulative printed circuit board first layer having a first side and a second side;   a first substantially conductive surface disposed on the first side of the printed circuit board;   a second substantially conductive surface disposed on the second side of the printed circuit board; and   wherein the first and second substantially conductive surfaces are of substantially the same size and shape and are in a substantially opposed relation.   
     
     
       16. The capacitor of claim 15, further comprising a first substantially conductive path coupled to a vertex of the first substantially conductive surface and a second substantially conductive path coupled to a vertex of the second substantially conductive surface. 
     
     
       17. A method of producing a capacitor, comprising the steps of: etching a first substantially conductive surface on a first side of a substantially insulative printed circuit board, the first substantially conductive surface being substantially polygonal in shape;   etching a second substantially conductive surface on a second side of the substantially insulative printed circuit board in a position substantially oppositionally disposed from the first substantially conductive surface, the second substantially conductive surface being substantially polygonal in shape; and   electrically coupling a first substantially conductive path to a vertex of the first substantially conductive surface, and electrically coupling a second substantially conductive path to a vertex of the second substantially conductive surface.   
     
     
       18. The method of claim 17, wherein the step of electrically coupling the first substantially conductive path to a vertex of the first substantially conductive surface comprises the step of etching a first conductive path to the first substantially conductive surface, and the step of electrically coupling the second substantially conductive path to a vertex of the second substantially conductive surface comprises the step of etching a second conductive path to the second substantially conductive surface. 
     
     
       19. The method of claim 17, wherein the step of electrically coupling a first substantially conductive path to a vertex of the first substantially conductive surface and electrically coupling a second substantially conductive path to a vertex of the second substantially conductive surface comprises the steps of: affixing a substantially insulative printed circuit board second layer having a first via therethrough to a first side of the printed circuit board first layer, wherein the first via is disposed adjacent to a vertex of the first substantially conductive surface, and etching the printed circuit board second layer to form the first substantially conductive path to the first via; and   affixing a substantially insulative printed circuit board third layer having a second via therethrough to a second side of the printed circuit board first layer, wherein the second via is disposed adjacent to a vertex of the second substantially conductive surface, and etching the printed circuit board third layer to form the second substantially conductive path to the second via.   
     
     
       20. The method of claim 17, wherein the step of electrically coupling a first substantially conductive path to a vertex of the first substantially conductive surface and electrically coupling a substantially conductive path to a vertex of the second conductive surface comprises the steps of: etching a substantially insulative printed circuit board second layer to form a first substantially conductive path;   etching a substantially insulative printed circuit board third layer to form a second substantially conductive path;   affixing the substantially insulative printed circuit board second layer to a first side of the printed circuit board first layer;   affixing the substantially insulative printed circuit board third layer to a second side of the printed circuit board first layer;   creating a first via through the substantially insulative printed circuit board first and second layers to electrically couple the vertex of the first substantially conductive surface and the first substantially conductive path; and   creating a second via through the substantially insulative printed circuit board first and third layers to electrically couple the vertex of the second substantially conductive surface and the second substantially conductive path.   
     
     
       21. A capacitor, formed by performing the steps of: etching a first substantially conductive surface on a first side of a substantially insulative printed circuit board, the first substantially conductive surface being substantially polygonal in shape;   etching a second substantially conductive surface on a second side of the substantially insulative printed circuit board in a position substantially oppositionally disposed from the first substantially conductive surface, the second substantially conductive surface being substantially polygonal in shape;   electrically coupling a first substantially conductive path to a vertex of the first substantially conductive surface; and   electrically coupling a second substantially conductive path to a vertex of the second substantially conductive surface.   
     
     
       22. The capacitor of claim 21, wherein the step of electrically coupling the first substantially conductive path to a vertex of the first substantially conductive surface comprises the step of etching a first conductive path to the first substantially conductive surface, and the step of electrically coupling the second substantially conductive path to a vertex of the second substantially conductive surface comprises the step of etching a second conductive path to the second substantially conductive surface. 
     
     
       23. The capacitor of claim 21, wherein the step of electrically coupling a first substantially conductive path to a vertex of the first substantially conductive surface comprises the steps of: affixing a substantially insulative printed circuit board second layer having a first via therethrough to a first side of the printed circuit board first layer, wherein the first via is disposed adjacent to the vertex of the first substantially conductive surface;   affixing a substantially insulative printed circuit board third layer having a second via therethrough to a second side of the printed circuit board first layer, wherein the second via is disposed adjacent to the vertex of the second substantially conductive surface;   etching the printed circuit board second layer to form the first substantially conductive path to the first via; and   etching the printed circuit board third layer to form the first substantially conductive path to the second via.