Integrated circuit and test method therefor

Abstract

In a mixed signal integrated circuit containing both an analog core circuit and a digital core circuit, a plurality of dedicated analog boundary scan cells disposed around the analog core circuit are connected in series by a dedicated analog boundary scan path. A plurality of dedicated digital boundary scan cells disposed around a digital core circuit are connected in series by a dedicated digital boundary scan path. The analog and digital boundary scan paths are independent of each other. In testing the analog or digital core circuit, the boundary scan path dedicated thereto is selected so that sets of test control data or test data are shifted only in the boundary scan cells dedicated thereto. As a consequence, a test pattern is shortened and the analog or digital core circuit can efficiently be tested in a shorter period of time.

We claim: 
     
       1. An integrated circuit comprising: an analog circuit and a digital circuit;   a plurality of analog boundary scan cells each connected to said analog circuit to receive test control data for bringing the analog circuit into a testable state;   a plurality of digital boundary scan cells each connected to said digital circuit to input test data to the digital circuit or receive a test result outputted from said digital circuit;   an analog boundary scan path for connecting in series only said analog boundary scan cells;   a digital boundary scan path for connecting in series only said digital boundary scan cells;   another analog circuit;   a plurality of other analog boundary scan cells connected to said other analog circuit to receive another test control data for bringing the other analog circuit into the testable state;   another analog boundary scan path for connecting in series only said other analog boundary scan cells;   a switch connected to respective leading points of said analog boundary scan path and said other analog boundary scan path; and   another switch connected to respective terminal points of said analog boundary scan path and said other analog boundary scan path.   
     
     
       2. An integrated circuit according to claim 1, further comprising: a test controller for testing said two analog circuits and said digital circuit, said test controller controlling said two switches.   
     
     
       3. An integrated circuit comprising: an analog circuit and a digital circuit;   a plurality of analog boundary scan cells each connected to said analog circuit to receive test control data for bringing the analog circuit into a testable state;   a plurality of digital boundary scan cells each connected to said digital circuit to input test data to the digital circuit or receive a test result outputted from said digital circuit;   an analog boundary scan path for connecting in series only said analog boundary scan cells;   a digital boundary scan path for connecting in series only said digital boundary scan cells;   another digital circuit;   a plurality of other digital boundary scan cells connected to said other digital circuit to input still another test data to the other digital circuit or receive a test result outputted from the other digital circuit;   another digital boundary scan path for connecting in series only said other digital boundary scan cells;   a switch connected to respective leading points of said digital boundary scan path and said other digital boundary scan path; and   another switch connected to respective terminal points of said digital boundary scan path and said other digital boundary scan path.   
     
     
       4. An integrated circuit according to claim 3, further comprising: a test controller for testing said analog circuit and said two digital circuits, said test controller controlling said two switches.   
     
     
       5. An integrated circuit comprising: an analog circuit and a digital circuit;   a plurality of analog boundary scan cells each connected to said analog circuit to receive test control data for bringing the analog circuit into a testable state;   a plurality of digital boundary scan cells each connected to said digital circuit to input test data to the digital circuit or receive a test result outputted from said digital circuit;   a first boundary scan path for connecting in series said analog boundary scan cells;   a second boundary scan path for connecting in series some of said digital boundary scan cells and a third boundary scan path for connecting in series the other of said digital boundary scan cells; and   first, second and third bypasses disposed in parallel with said first, second, and third boundary scan paths, respectively,   said first boundary scan path and said second and third bypasses being connected in series to form an analog boundary scan path for connecting in series only said analog boundary scan cells,   said second and third boundary scan paths and said first bypass being connected in series to form a digital boundary scan path for connecting in series only said digital boundary scan cells.   
     
     
       6. An integrated circuit according to claim 5, further comprising: a switch connected to respective one ends of said first boundary scan path and said first bypass and to respective one ends of said second boundary scan path and said second bypass; and   another switch connected to the respective other ends of said first boundary scan path and said first bypass and to the respective other ends of said third boundary scan path and said third bypass.   
     
     
       7. An integrated circuit according to claim 6, further comprising: a test controller for testing said analog circuit and said digital circuit, said test controller controlling said two switches such that: in testing said analog circuit, one end of said first boundary scan path is connected to one end of said second bypass and the other end of said first boundary scan path is connected to one end of said third bypass, and   in testing said digital circuit, one end of said second boundary scan path is connected to one end of said first bypass and the other end of said first bypass is connected to one end of said third boundary scan path.     
     
     
       8. An integrated circuit according to claim 5, wherein at least one of said second and third boundary scan paths is divided into a plurality of boundary scan paths disposed in parallel, each of the boundary scan paths connecting in series some of the digital boundary scan cells. 
     
     
       9. An integrated circuit comprising: an analog circuit and a digital circuit;   a plurality of analog boundary scan cells each connected to said analog circuit to receive test control data for bringing the analog circuit into a testable state;   a plurality of digital boundary scan cells each connected to said digital circuit to input test data to the digital circuit or receive a test result outputted from said digital circuit;   a first boundary scan path for connecting in series said digital boundary scan cells;   a second boundary scan path for connecting in series some of said analog boundary scan calls and a third boundary scan path for connecting in series the other of said analog boundary scan cells; and   first, second and third bypasses disposed in parallel with said first, second and third boundary scan paths, respectively,   said first boundary scan path and said second and third bypasses being connected in series to form a digital boundary scan path for connecting in series only said digital boundary scan cells,   said second and third boundary scan paths and said first bypass being connected in series to form an analog boundary scan path for connecting in series only said analog boundary scan cells.   
     
     
       10. An integrated circuit according to claim 9, further comprising: a switch connected to respective one ends of said first boundary scan path and said first bypass and to respective one ends of said second boundary scan path and said second bypass; and   another switch connected to the respective other ends of said first boundary scan path and said first bypass and to the respective other ends of said third boundary scan path and said third bypass.   
     
     
       11. An integrated circuit according to claim 10, further comprising: a test controller for testing said analog circuit and said digital circuit, said test controller controlling said two switches such that: in testing said digital circuit, one end of said first boundary scan path is connected to one end of said second bypass and the other end of said first boundary scan path is connected to one end of said third bypass, and   in testing said analog circuit, one end of said second boundary scan path is connected to one end of said first bypass and the other end of said first bypass is connected to one end of said third boundary scan path.     
     
     
       12. An integrated circuit according to claim 9, wherein at least one of said second and third boundary scan paths is divided into a plurality of boundary scan paths disposed in parallel, each of the boundary scan paths connecting in series some of the analog boundary scan cells. 
     
     
       13. An integrated circuit according to claim 5 or 9, further comprising: a plurality of connecting lines for connecting said analog circuit and said digital circuit;   scan cells disposed to intervene said respective connecting lines; and   a fourth boundary scan path for connecting in series said scan cells, said fourth boundary scan path composing a part of said analog or digital boundary scan path.   
     
     
       14. An integrated circuit according to claim 13, further comprising: a fourth bypass disposed in parallel with said fourth boundary scan path;   a switch for connecting one end of either of said fourth boundary scan path and said fourth bypass to the first boundary scan path or to the first bypass; and   another switch for connecting the other end of either of said fourth boundary scan path and said fourth bypass to the third boundary scan path or to the third bypass.   
     
     
       15. An integrated circuit according to claim 14, further comprising a test controller for testing said analog circuit and said digital circuit, said test controller controlling said two switches.