Charge coupled device

Abstract

A charge coupled device and a manufacturing method therefor are provided. The charge coupled device has a transfer electrode portion having a first gate electrode, a second gate electrode having an end portion partially overlapping an end portion of the first gate electrode, and a third gate electrode having one end portion partially overlapping the other end portion of the first gate electrode and the other end portion thereof partially overlapping the other end portion of the second gate electrode. The charge coupled device also has a charge transfer portion located in a semiconductor substrate under the first, second and third gate electrodes, which includes a first potential area formed in the semiconductor substrate under the second gate electrode and a second potential area formed in the semiconductor substrate under the third gate electrode. The charge coupled device further has a clock portion which includes a first clock terminal connected to the first and third gate electrodes, and a second clock terminal connected to the second gate electrode. This charge coupled device may prevent unnecessary local potential barriers or wells produced by a misalignment, and thus may provide increased charge transfer efficiency.

What is claimed is: 
     
       1. A charge coupled device comprising: a transfer electrode portion having not more than a first gate electrode, a second gate electrode and a third gate electrode wherein said second gate electrode and said third gate electrode partially overlap said first gate electrode;   a charge transfer portion located in a semiconductor substrate under said first, second and third gate electrodes;   a clock portion having a first clock terminal connected to said first and third gate electrodes, and a second clock terminal connected to said second gate electrode.   
     
     
       2. The charge coupled device according to claim 1, further comprising first and second potential areas formed in said semiconductor substrate, wherein said first potential area is formed under said second gate electrode and wherein said second potential area is formed under said third gate electrode. 
     
     
       3. The charge coupled device according to claim 2, wherein an end portion of said first potential area is substantially aligned with an end portion of said first gate electrode and the other end portion of said first potential area is aligned with a middle portion of said second gate electrode, and wherein an end portion of said second potential area is substantially aligned with the other end portion of said first gate electrode. 
     
     
       4. The charge coupled device according to claim 3, wherein the size of said first potential area is the same as that of said second potential area. 
     
     
       5. A charge coupled device comprising: a transfer electrode portion having not more than a first gate electrode, a second gate electrode and a third gate electrode;   a charge transfer portion located in a semiconductor substrate under said first to third gate electrodes, and having a first potential area formed in said semiconductor substrate under said second gate electrode and a second potential area formed in said semiconductor substrate under said third gate electrode; and   a first clock terminal connected to said first and third gate electrodes, and a second clock terminal connected to said second gate electrode;   wherein said second gate electrode has a first end overlapping a first end of said first gate electrode and a second end which is disposed between said charge transfer portion and at least part of a gate electrode of an adjacent group of first, second and third gate electrodes; and   wherein said third gate electrode has a first end overlapping a second end of said first gate electrode.   
     
     
       6. A charge coupled device as claimed in claim 5, wherein the size of said first potential area is the same as that of said second potential area. 
     
     
       7. A charge coupled device as claimed in claim 6, wherein an end portion of said first potential area is aligned with an end portion of said first gate electrode and the other end portion of said first potential area is aligned with a middle portion of said second gate electrode, and the end portions of said second potential area are aligned with the other end portion of said first gate electrode and an end portion of a gate electrode in an adjacent group of first, second and third gate electrodes. 
     
     
       8. A charge coupled device comprising: a transfer electrode portion having not more than a first gate electrode, a second gate electrode and a third gate electrode wherein said second gate electrode and said third gate electrode partially overlap said first gate electrode;   a charge transfer portion located in a semiconductor substrate under said first, second and third gate electrodes;   a clock portion having a first clock terminal connected to said first and third gate electrodes, and a second clock terminal connected to said second gate electrode; and   an insulating layer disposed between said transfer electrode portion and said charge transfer portion, wherein a first end portion of said second gate electrode partially overlaps said first gate electrode and wherein a second end portion of said second gate electrode contacts said insulating layer and wherein said third gate electrode partially overlaps said first gate electrode.   
     
     
       9. A charge coupled device comprising: a transfer electrode portion having a plurality of groups of first, second and third gate electrodes, wherein in each of said groups a first end of said second gate electrode overlaps a first end of said first gate electrode, a first end of said third gate electrode overlaps a second end of said first gate electrode and a second end of said third gate electrode overlaps a second end of the second gate electrode in an adjacent group of first, second and third gate electrodes;   a charge transfer portion located in a semiconductor substrate under said plurality of groups of first, second and third gate electrodes;   first and second clock terminals connected to said transfer electrode portion;   a plurality of first and second potential areas formed in said semiconductor substrate, wherein said first potential areas are formed under said second gate electrodes and wherein said second potential areas are formed under said third gate electrodes; and   wherein in each of said groups an end portion of said first potential area is aligned with an end portion of said first gate electrode, and wherein the end portions of said second potential area are aligned with the other end portion of said first gate electrode and an end portion of the second gate electrode in an adjacent group of first, second and third gate electrodes.   
     
     
       10. The charge coupled device according to claim 9, wherein said first clock terminal is connected to each of said first and third gate electrodes in said plurality of groups of first, second and third gate electrodes, and said second clock terminal is connected to each of said second gate electrodes in said plurality of groups of first, second and third gate electrodes. 
     
     
       11. The charge coupled device according to claim 9, wherein the first gate electrodes in each group are shaped substantially the same, wherein the second gate electrodes in each group are shaped substantially the same and wherein the third gate electrodes in each group are shaped substantially the same.