Ferroelectric memory device and method of reducing imprint effect thereof

Abstract

A ferroelectric memory device which is less likely to be affected with imprint effect and a highly effective method for reducing the imprint effect of the ferroelectric memory cell. A data reversing latch circuit is disposed between a pair of bit lines BL0 and /BL0 and has capacitors C1 and C2. When data is read, it is possible to store the potentials on the pair of bit lines BL0 and /BL0 as charges in the capacitors C1 and C2, and to reverse the high-low relationship between the potentials on the bit lines BL0 and /BL0 and then back to the original relationship according to stored charges in the capacitors C1 and C2. In this way, the imprint effect of the memory cell MO may be automatically reduced when data is read by reversing the data in the memory MO connected to the bit lines BL0 and /BL0 and again reversing the data back to normal.

What is claimed is: 
     
       1. A ferroelectric memory device comprising at least one ferroelectric memory cell storing information by holding a polarized state corresponding to said information, and means for performing steps of changing the polarized state of said ferroelectric memory cell to a state which is different from the polarized state to be held, and changing the polarized state thereof back to the original polarized state, wherein said performing means provides an imprint effect reducing operation. 
     
     
       2. A ferroelectric memory device as claimed in claim 1, wherein a plurality of said ferroelectric memory cells are arranged in rows and columns so that a desired ferroelectric memory cell may be selected from among said ferroelectric memory cells arranged in rows and columns, and wherein said performing means provides the imprint effect reducing operation to correspond to data communication lines which are provided for writing data to or reading data from said selected ferroelectric memory cell, so that, when information is written or read, the imprint effect reducing operation is performed for a specified number of times for said ferroelectric memory cell selected from among said ferroelectric memory cells arranged in rows and columns. 
     
     
       3. A ferroelectric memory device as claimed in claim 1, wherein a plurality of said ferroelectric memory cells are arranged in rows and columns so that a desired ferroelectric memory cell may be selected from among said ferroelectric memory cells arranged in rows and columns, and wherein said performing means provides the imprint effect reducing operation to correspond to each column of the row-and-column arrangement, so that, when information is written or read, the imprint effect reducing operation is performed for a specified number of times for said ferroelectric memory cells included in the row to which said ferroelectric memory cell selected from among said ferroelectric memory cells arranged in rows and columns belongs. 
     
     
       4. A ferroelectric memory device as claimed in claim 1, wherein said performing means comprises at least one auxiliary memory cell provided for storing auxiliary information corresponding to the polarized states to be held of said ferroelectric memory cell, so that the imprint effect reducing operation is performed according the contents of the auxiliary information stored in said auxiliary memory cell. 
     
     
       5. A ferroelectric memory device of claim 4, wherein a plurality of said ferroelectric memory cells are arranged in rows and columns so that a desired ferroelectric memory cell may be selected from among said ferroelectric memory cells arranged in rows and columns, and wherein said performing means provides the imprint effect reducing operation to correspond to said data communication lines which are provided for writing data to or reading data from said selected ferroelectric memory cell, so that, when information is written or read, the imprint effect reducing operation is performed for a specified number of times for said ferroelectric memory cell selected from among said ferroelectric memory cells arranged in rows and columns. 
     
     
       6. A ferroelectric memory device as claimed in claim 4, wherein a plurality of said ferroelectric memory cells are arranged in rows and columns so that a desired ferroelectric memory cell may be selected from among said ferroelectric memory cells arranged in rows and columns, and wherein said performing means provides the imprint effect reducing operation to correspond to each column of the row-and-column arrangement, so that, when information is written or read, the imprint effect reducing operation is performed for a specified number of times for said ferroelectric memory cells included in the row to which said ferroelectric memory cell selected from among said ferroelectric memory cells arranged in rows and columns belongs. 
     
     
       7. A ferroelectric memory device as claimed in claim 4, wherein said ferroelectric memory cell is provided with first and second ferroelectric memory elements for holding polarized states different from each other, and wherein said auxiliary memory cell is provided with a first auxiliary memory element for storing information corresponding to the polarized state to be held in said first ferroelectric memory element, and with a second auxiliary memory element for storing information corresponding to the polarized state to be held in said second ferroelectric memory element, the polarized state of said first ferroelectric memory element being changed according to said auxiliary information stored in said second auxiliary memory element with the polarized state of said second ferroelectric memory element being changed according to the auxiliary information stored in said first auxiliary memory element, and the polarized state of said first ferroelectric memory element being subsequently changed back to the original state according to the auxiliary information stored in said first auxiliary memory element and the polarized state of said second ferroelectric memory element being changed back to the original state according to the auxiliary information stored in said second auxiliary memory element.   
     
     
       8. A ferroelectric memory device as claimed in claim 7, wherein a plurality of said ferroelectric memory cells are arranged in rows and columns so that a desired ferroelectric memory cell may be selected from among said ferroelectric memory cells arranged in rows and columns, and wherein said performing means provides the imprint effect reducing operation to correspond to said data communication lines which are provided for writing data to or reading data from said selected ferroelectric memory cell, so that, when information is written or read, the imprint effect reducing operation is performed for a specified number of times for said ferroelectric memory cell selected from among said ferroelectric memory cells arranged in rows and columns. 
     
     
       9. A ferroelectric memory device as claimed in claim 7, wherein a plurality of said ferroelectric memory cells are arranged in rows and columns so that a desired ferroelectric memory cell may be selected from among said ferroelectric memory cells arranged in rows and columns, and wherein said performing means provides the imprint effect reducing operation to correspond to each column of the row-and-column arrangement, so that, when information is written or read, the imprint effect reducing operation is performed for a specified number of times for said ferroelectric memory cells included in the row to which said ferroelectric memory cell selected from among said ferroelectric memory cells arranged in rows and columns belongs. 
     
     
       10. A ferroelectric memory device as claimed in claim 7, wherein each of said first and said second ferroelectric memory elements is provided with a ferroelectric capacitor, and wherein each of said first and said second auxiliary memory elements is provided with a capacitor, the polarized state of said first ferroelectric memory element being changed according to the auxiliary information stored in said second auxiliary memory element by interconnecting said second auxiliary memory element and said first ferroelectric memory element through an electric communication path, with the polarized state of said second ferroelectric memory element being changed according to the auxiliary information stored in said first auxiliary memory element by interconnecting said first auxiliary memory element and said second ferroelectric memory element through said electric communication path, and polarized state of said first ferroelectric memory element being subsequently changed back to the original state according to the auxiliary information stored in said first auxiliary memory element by interconnecting said first auxiliary memory element and said first ferroelectric memory element through said electric communication path, and the polarized state of said second ferroelectric memory element being changed back to the original state according to the auxiliary information stored in said second auxiliary memory element by interconnecting said second auxiliary memory cell and said second ferroelectric memory element through said electric communication path. 
     
     
       11. A ferroelectric memory device as claimed in claim 10, wherein a plurality of said ferroelectric memory cells are arranged in rows and columns so that a desired ferroelectric memory cell may be selected from among said ferroelectric memory cells arranged in rows and columns, and wherein said performing means provides the imprint effect reducing operation to correspond to said data communication lines which are provided for writing data to or reading data from said selected ferroelectric memory cell, so that, when information is written or read, the imprint effect reducing operation is performed for a specified number of times for said ferroelectric memory cell selected from among said ferroelectric memory cells arranged in rows and columns. 
     
     
       12. A ferroelectric memory device as claimed in claim 10, wherein a plurality of said ferroelectric memory cells are arranged in rows and columns so that a desired ferroelectric memory cell may be selected from among said ferroelectric memory cells arranged in rows and columns, and wherein said performing means provides the imprint effect reducing operation to correspond to each column of the row-and-column arrangement, so that, when information is written or read, the imprint effect reducing operation is performed for a specified number of times for said ferroelectric memory cells included in the row to which said ferroelectric memory cell selected from among said ferroelectric memory cells arranged in rows and columns belongs. 
     
     
       13. A ferroelectric memory device as claimed in claim 10, wherein said electric communication path includes a first bit line and a second bit line, one end of said ferroelectric capacitor constituting said first ferroelectric memory element being substantially connected through a first transistor to said first bit line, one end of said ferroelectric capacitor constituting said second ferroelectric memory element being substantially connected through a second transistor to said second bit line, with the other end of each of said paired ferroelectric capacitors being connected to a plate line. 
     
     
       14. A ferroelectric memory device as claimed in claim 13, wherein a plurality of said ferroelectric memory cells are arranged in rows and columns so that a desired ferroelectric memory cell may be selected from among said ferroelectric memory cells arranged in rows and columns, and wherein said performing means provides the imprint effect reducing operation to correspond to said data communication lines which are provided for writing data to or reading data from said selected ferroelectric memory cell, so that, when information is written or read, the imprint effect reducing operation is performed for a specified number of times for said ferroelectric memory cell selected from among said ferroelectric memory cells arranged in rows and columns. 
     
     
       15. A ferroelectric memory device as claimed in claim 13, wherein a plurality of said ferroelectric memory cells are arranged in rows and columns so that a desired ferroelectric memory cell may be selected from among said ferroelectric memory cells arranged in rows and columns, and wherein said performing means provides the imprint effect reducing operation to correspond to each column of the row-and-column arrangement, so that, when information is written or read, the imprint effect reducing operation is performed for a specified number of times for said ferroelectric memory cells included in the row to which said ferroelectric memory cell selected from among said ferroelectric memory cells arranged in rows and columns belongs. 
     
     
       16. A ferroelectric memory device as claimed in claim 13, wherein said performing means comprises a bridge circuit having four arms each provided with a transistor, one end of said capacitor constituting said first auxiliary memory element and one end of said capacitor constituting said second auxiliary memory element being substantially connected respectively to one diagonally opposite pair of corners of said bridge circuit, with the other ends of said pair of capacitors being substantially grounded, and said first and said second bit lines being respectively connected to the other diagonally opposite corners of said bridge circuit. 
     
     
       17. A ferroelectric memory device as claimed in claim 16, wherein a plurality of said ferroelectric memory cells are arranged in rows and columns so that a desired ferroelectric memory cell may be selected from among said ferroelectric memory cells arranged in rows and columns, and wherein said performing means provides the imprint effect reducing operation to correspond to said data communication lines which are provided for writing data to or reading data from said selected ferroelectric memory cell, so that, when information is written or read, the imprint effect reducing operation is performed for a specified number of times for said ferroelectric memory cell selected from among said ferroelectric memory cells arranged in rows and columns. 
     
     
       18. A ferroelectric memory device as claimed in claim 16, wherein a plurality of said ferroelectric memory cells are arranged in rows and columns so that a desired ferroelectric memory cell may be selected from among said ferroelectric memory cells arranged in rows and columns, and wherein said performing means provides the imprint effect reducing operation to correspond to each column of the row-and-column arrangement, so that, when information is written or read, the imprint effect reducing operation is performed for a specified number of times for said ferroelectric memory cells included in the row to which said ferroelectric memory cell selected from among said ferroelectric memory cells arranged in rows and columns belongs. 
     
     
       19. A method of reducing imprint effect of a ferroelectric memory cell capable of storing information by holding a polarized state corresponding to said information, said method comprising performing, when said information is written or read, an operation for a specified number of times, said operation comprising the steps of setting said ferroelectric memory cell to a state which is different from said polarized state to be held and then setting said ferroelectric memory cell back to said polarized state to be held.