DRAM configuration in PLDs

Abstract

Described are dynamic memory cells for use in FPGAs. Each memory cell includes a dynamic memory element that occupies less chip area than conventional static memory elements and that can be implemented using standard CMOS processes. In one embodiment, a conventional access transistor is connected to a pass transistor via a CMOS inverter. The CMOS inverter includes a pair of complementary MOS transistors sharing a common gate connection, and therefore exhibiting a combined gate capacitance. This gate capacitance at the input of the inverter supplements or replaces the capacitor normally required in conventional dynamic memory cells. Another embodiment uses the parasitic gate capacitance of a pass transistor for dynamic data storage. This embodiment requires that the voltage levels on the source and drain of the pass transistor be controlled during write and refresh operations to ensure that the gate capacitance of pass transistor stores an appropriate level of charge.

I claim: 
     
       1. A dynamic memory cell for a programmable logic device, the memory cell comprising: an access transistor having: a control terminal connected to a memory-access line;   a first current-handling terminal connected to a memory-refresh line; and   a second current-handling terminal;     an inverter having: an input terminal; and   an output terminal, the input terminal being connected to the second current-handling terminal of the access transistor, wherein the input terminal of the inverter exhibits a parasitic capacitance;       a pass transistor having: a control terminal connected to the output terminal of the inverter;   a first current-handling terminal connected to a first interconnect segment; and   a second current-handling terminal connected to a second interconnect segment, wherein the first and second interconnect segments are selectively connected by presenting a specified voltage level on the control terminal of the pass transistor; and     a memory refresh circuit having: an output terminal connected to the control terminal of the access transistor, the memory refresh circuit configured to periodically bias the access transistor on to refresh the voltage level on the input terminal of the inverter,         wherein the capacitance of the input terminal of the inverter is selected to retain at least a minimum level of charge between the periodic biasing of the access transistor.   
     
     
       2. The memory cell of claim 1, wherein the inverter further includes: a first MOS transistor having a gate terminal connected to the second current-handling terminal of the access transistor; and   a second MOS transistor having a gate terminal connected to the second current-handling terminal of the access transistor,   wherein the capacitance associated with the input terminal of the inverter is the collective capacitance of the gates of the first and second MOS transistors.   
     
     
       3. The memory cell of claim 2, wherein the first MOS transistor is a PMOS transistor and the second MOS transistor is an NMOS transistor. 
     
     
       4. The memory cell of claim 3, wherein the inverter is a CMOS inverter. 
     
     
       5. A dynamic memory for a programmable logic device, the memory comprising: a plurality of memory cells, each memory cell including: an access transistor having: a control terminal connected to a memory-access line;   a first current-handling terminal connected to a memory-refresh line; and   a second current-handling terminal;     a pass transistor having: a control terminal connected to the second current-handling terminal of the access transistor;   a first current-handling terminal connected to a first interconnect segment and electrically insulated from the pass-transistor control terminal; and   a second current-handling terminal connected to a second interconnect segment and electrically insulated from the pass-transistor control terminal,   wherein the first and second interconnect segments are selectively connected by presenting a specified voltage level on the control terminal of the pass transistor; and       a memory refresh circuit having an output terminal connected to the control terminal of the access transistor, the memory refresh circuit configured to periodically bias the access transistor on to refresh the voltage level on the control terminal of the pass transistor.   
     
     
       6. A method of writing binary data to a memory cell in a programmable logic device, wherein the memory cell comprises an access transistor having a control terminal connected to a word line, a first current-handling terminal connected to a bit line, and a second current-handling terminal connected to the gate of an MOS pass transistor, the method comprising: writing data of a first logic level or a second logic level to the gate of the pass transistor;   when writing data of the first logic level, holding the source and the drain of the pass transistor to a first voltage level; and   holding the gate of the pass transistor to a second voltage level different from the first voltage level; and   when writing data of the second logic level, holding the source and the drain of the pass transistor to the second voltage level; and   holding the gate of the pass transistor to the first voltage level.       
     
     
       7. The method of claim 6, wherein the pass transistor exhibits a gate capacitance, the method further comprising: determining a refresh rate of the gate capacitance based on a value of the gate capacitance and a charge-leakage rate of the gate capacitance; and refreshing the voltage level on the gate capacitance at the refresh rate during operation of the programmable logic device.