Synchronous control apparatus

Abstract

A synchronous control device having a memory 101 for storing block data blocked in terms of a pre-set data amount, a clock generating circuit 102 for generating input side clocks which are based on a data rate to be synchronized, and a memory control unit 103 for generating output side clocks C out responsive to input side clocks C in from the clock generating circuit 102. The memory 101 stores the block data on the block basis, based on the input side clocks C in from the clock generating circuit 103, and outputs the stored block data based on the output side clocks C out from the memory control circuit 103. The memory control circuit 103 detects a difference between the input data volume and the output side data volume in the memory 101 for varying the speed of the output side clocks responsive to the amount of the detected difference so that the output side clocks will be synchronized with the input side clocks C in from the clock generating circuit 103.

We claim: 
     
       1. A synchronous control apparatus comprising: memory means for storing block data blocked in terms of a pre-set data amount, clock generating means for generating an input side clock which is based on a data rate to be synchronized, and control means for generating an output side clock responsive to the input side clock from said clock generating means; wherein   said memory means stores the block data on a block by block basis, based on the input side clock from said clock generating means, and outputs the stored block data based on the output side clock from said control means; and wherein   said control means detects a difference between the input data volume and the output side data volume in said memory means for varying the speed of the output side clock responsive to the amount of the detected difference.   
     
     
       2. The synchronous control apparatus as claimed in claim 1 wherein said control means varies the speed of the output side clock significantly and slightly if the difference is of a larger or a smaller value, respectively. 
     
     
       3. The synchronous control apparatus as claimed in claim 1 wherein said memory means stores speech signals and wherein said clock generating means generates the input side clock which is based on an image signal reproducing speed. 
     
     
       4. The synchronous control apparatus as claimed in claim 3, wherein said image signal reproducing speed is variable, and said input side clock thereby having a variable speed. 
     
     
       5. A synchronous control apparatus comprising: memory means for storing block data blocked in terms of a pre-set data amount, clock generating means for generating an input side clock which is based on a data rate to be synchronized, and control means for generating an output side clock responsive to the input side clock from said clock generating means; wherein   said memory means stores the block data on a block by block basis, based on the input side clock from said clock generating means, and outputs the stored block data based on the output side clock from said control means; and wherein   said control means detects an amount of data currently stored in the memory means, and varies the speed of the output side clock responsive to the detected amount of currently stored data, the output side clock speed variation being correlated with a detected deviation from a predetermined amount of stored data.   
     
     
       6. The synchronous control apparatus as claimed in claim 5, wherein said predetermined amount of stored data is an amount of data storable in one half of said memory means. 
     
     
       7. The synchronous control apparatus as claimed in claim 5 wherein said control means varies the speed of the output side clock significantly and slightly if the detected deviation is of a larger or a smaller value, respectively. 
     
     
       8. The synchronous control apparatus as claimed in claim 5 wherein said memory means stores speech signals and wherein said clock generating means generates the input side clock which is based on an image signal reproducing speed. 
     
     
       9. The synchronous control apparatus as claimed in claim 8, wherein said image signal reproducing speed is variable, and said input side clock thereby having a variable speed. 
     
     
       10. A synchronous control apparatus comprising: a memory for temporarily storing block data;   a clock generator operable to generate an input side clock having a variable speed controlling a rate at which data is input to said memory, said variable speed being synchronized with a reproduction rate associated with reproduction of other information; and   a memory controller operable to detect an amount of data currently stored within said memory, and to generate an output side clock having a speed controlling a rate of data retrieved from said memory;   wherein said output side clock speed is varied based on the detected amount of currently stored data, and is correlated with a detected deviation from a predetermined amount of stored data.   
     
     
       11. The synchronous control apparatus as claimed in claim 10, wherein said predetermined amount of stored data is an amount of data storable in one half of said memory. 
     
     
       12. The synchronous control apparatus as claimed in claim 10 wherein said memory controller varies the speed of the output side clock significantly and slightly if the detected deviation is of a larger or a smaller value, respectively. 
     
     
       13. The synchronous control apparatus as claimed in claim 10 wherein said memory stores speech signals and wherein said reproduction rate associated with reproduction of other information is a variable reproduction rate for an image signal associated with said speech signals.