Integrated circuit memory devices having page flag cells which indicate the true or non-true state of page data therein and methods of operating the same

Abstract

Integrated circuit memory devices with page copy flag cells include an array of memory cells and a plurality of flag cells coupled thereto which retain a flag to indicate whether a respective page of memory cells contains data copied in an inverted format from another page of memory cells. The memory cells and flag cells may comprise EEPROM cells and each page of memory cells preferably shares a word line with a respective flag cell. The flag may constitute a logic 1 (or logic 0) signal stored in the flag EEPROM cell to indicate whether the data in the corresponding page of memory is a true or an inverted copy of a page of data copied from another page at a different address. A page buffer is also provided to retain data read from a page of memory and read from a corresponding flag cell, and an exclusive OR gate for inverting the data outputted by the page buffer if the flag has been set and passing the outputted data unchanged if the flag has not been set.

That which is claimed is: 
     
       1. An integrated circuit memory device, comprising: an array of memory cells arranged as a plurality of pages of memory cells electrically coupled to a respective plurality of word lines and a plurality of columns of memory cells electrically coupled to a respective plurality of bit lines;   a plurality of flag cells, each of said plurality of flag cells coupled to a respective one of the plurality of pages of memory cells by a respective word line and retaining a flag which indicates whether the respective one of the plurality of pages of memory cells contains data copied in an inverted format from another one of the plurality of pages of memory cells;   a page buffer, coupled to said array of memory cells and said plurality of flag cells, to retain data read from a page of memory cells and a respective flag cell; and   a data inverter, coupled to an output of said page buffer, to output an inverted copy of the read data if the respective flag cell contains a flag and pass the read data unchanged if the respective flag cell does not contain a flag;   wherein each of the plurality of pages of memory cells shares a word line with a respective flag cell in said plurality of flag cells.   
     
     
       2. The integrated circuit memory device of claim 1, wherein said array of memory cells and said plurality of flag cells comprise EEPROM cells. 
     
     
       3. The integrated circuit memory device of claim 1, wherein said data inverter comprises an exclusive OR gate.