Dynamic random-access memory having a hierarchical data path

Abstract

A semiconductor dynamic random-access memory (DRAM) device embodying numerous features that collectively and/or individually prove beneficial and advantageous with regard to such considerations as density, power consumption, speed, and redundancyis disclosed. The device is a 64 Mbit DRAM comprising eight substantially identical 8 Mbit partial array blocks (PABs), each pair of PABs comprising a 16 Mbit quadrant of the device. Between the top two quadrants and between the bottom two quadrants are column blocks containing I/O read/write circuitry, column redundancy fuses, and column decode circuitry. Column select lines originate from the column blocks and extend right and left across the width of each quadrant. Each PAB comprises eight substantially identical 1Mbit sub-array blocks (SABs). Associated with each SAB are a plurality of local row decoder circuits functioning to receive partially decoded row addresses from a column predecoder circuit and generating local row addresses supplied to the SAB with which they are associated. A hierarchical data path is provided wherein a plurality of multiplexers are distributed throughout each SAB, these multiplexers functioning to selectively couple sense amplifier output signals to local data I/O lines associated with each SAB. In one embodiment, the data path multiplexers are physically disposed within gaps defined by adjacent ones of the local row address decoders distributed throughout each SAB.

What is claimed is: 
     
       1. A semiconductor memory device, comprising an array of rows and columns of memory cells each disposed at an intersection between a digit line and a word line, wherein said array of rows and columns of memory cells is subdivided into a plurality of substantially equivalent partial arrays of rows and columns of memory cells, said plurality of partial arrays physically arranged in a plurality of adjacent pairs of partial arrays such that each pair of partial arrays defines a substantially elongate intermediate area between the partial arrays of said each pair of partial arrays, and said partial arrays being further subdivided into a plurality of sub-arrays, said sub-arrays physically arranged in a plurality of adjacent pairs such that each pair of sub-arrays defines a substantially elongate intermediate area between the sub-arrays of each pair of sub-arrays, said memory device further comprising: a hierarchical decoding system comprising, for each of said plurality of adjacent pairs of partial arrays, row address predecoding circuitry, responsive to row address signals supplied to said device to generate a plurality of predecoded row address signals; and   a plurality of row decoder driver circuits, coupled to said row address predecoding circuitry, said row decoder driver circuits responsive to said predecoded row address signals to generate local row address signals;   a plurality of local row address decoding circuits, distributed throughout said sub arrays and each electrically coupled to one of said row decoder driver circuits to receive said local row address signals, said local row decoding circuits selectively responsive to said local row address signals to apply at least one word line driving signal to its associated subarray during a memory access cycle; and   a hierarchical data path, comprising: a plurality sense amplifiers, adapted to sense the presence or absence of charge in one of said memory cells and to produce a sense amplifier output signal reflecting said presence or absence of charge;   a plurality of multiplexers, distributed throughout said subarrays, each coupled to receive a plurality of said sense amplifier output signals, said multiplexers responsive to said local row address signals to selectively couple one of said plurality of sense amplifier output signals to a local input/output line associated with one of said subarrays.     
     
     
       2. A memory device in accordance with claim 1, wherein said multiplexers are physically disposed in gaps defined between adjacent ones of said local row address decoding circuits.