Overall VPP well form

Abstract

Realizing a reduction of the layout surface area by rendering unnecessary the region used for well isolation. In this DRAM, a triple well construction is used, and all of the regions for the unit memory cell array MA, the word line driver bank WDB, the sense amplifier bank SAB, and the cross area CR are surrounded by a lower layer N-type deep (deep layer) well 12. A back bias VPP corresponding to the power supply voltage of the word line driver is applied to the N well 14, and a back bias VBB corresponding to the characteristics of the memory cell are applied to the P well 16. In the N well 14, in regard to the P-type MOS transistors of the sense amplifier that undergo the substrate bias effect due to the back bias VPP, the threshold voltage is set to a low value so as to cancel that bias effect. Also, in the P well 16, in regard to the N-type MOS transistors of the sense amplifiers that undergo the substrate bias effect due to the back bias VBB, the threshold voltage is designed to a low value so as to cancel that bias effect.

We claim: 
     
       1. A semiconductor device having a semiconductor substrate of a first conductor type,   a semiconductor layer of a second conductor type that is formed on the above-mentioned semiconductor substrate,   one or multiple semiconductor regions of the first semiconductor type and one or multiple semiconductor regions of the second conductor type that are aligned on top of the above-mentioned semiconductor layer isolated from the above-mentioned semiconductor substrate,   one or multiple MOS transistors of the second semiconductor type that are formed within the respective semiconductor regions of the above-mentioned first semiconductor type,   one or multiple MOS transistors of the first semiconductor type that are formed within the respective semiconductor regions of the above-mentioned second semiconductor type,   along with applying a common first back bias to the respective semiconductor regions of the above-mentioned first conductor type, a common second back bias is applied to the above-mentioned semiconductor layer and the respective semiconductor regions of the above-mentioned second conductor type,   and along with being designed so that, in at least one of the semiconductor regions of the above-mentioned first conductor type, the threshold voltage for the MOS transistor of at least one of the above-mentioned MOS transistors of the second conductor type cancels the substrate bias by means of the above-mentioned first back bias, and in at least one of the semiconductor regions of the above-mentioned second conductor type, the threshold voltage for at least one of the MOS transistors of the above-mentioned first conductor type cancels the substrate bias effect by means of the above-mentioned second back bias.   
     
     
       2. The semiconductor device recorded in claim 1 wherein a single memory cell array section and a section of one or multiple peripheral circuit sections that are connected to the above-mentioned memory cell array section are contained within at least one of the semiconductor regions of the above-mentioned first conductor type, and is designed so that the threshold voltage of at least one of the MOS transistors of the above-mentioned second conductor type of the above-mentioned peripheral section cancels the substrate bias effect by means of the above-mentioned first back bias. 
     
     
       3. The semiconductor device recorded in claim 2 wherein the remaining portion of the above-mentioned peripheral circuit section is provided within the semiconductor region of the above-mentioned second conductor type that is adjacent to a portion of the region of the above-mentioned peripheral circuit that is formed within the semiconductor region of the above-mentioned first conductor type, and is designed so that the threshold voltage of at least one of the MOS transistors of the above-mentioned first conductor type of the above-mentioned peripheral circuit section cancels the substrate bias effect by means of the above-mentioned second back bias.