Real-time power conservation for computers

Abstract

A real-time power conservation apparatus and method for portable computers employs a monitor to determine whether a CPU may rest based upon a real-time sampling of the CPU activity level and to activate a hardware selector to carry out the monitor's determination. If the monitor determines the CPU may rest, the hardware selector reduces CPU clock time; if the CPU is to be active, the hardware selector returns the CPU to its previous high speed clock level. Switching back into full operation from its rest state occurs without a user having to request it and without any delay in the operation of the computer while waiting for the computer to return to a "ready" state. Furthermore, the monitor adjusts the performance level of the computer to manage power conservation in response to the real-time sampling of CPU activity. Such adjustments are accomplished within the CPU cycles and do not affect the user's perception of performance and do not affect any system application software executing on the computer.

We claim: 
     
       1. A device, comprising: a computer including a central processing unit (CPU);   a central processing unit activity detector;   means, responsive to said activity detector, for predicting an activity level within said computer; and   means for using predictions, from said means for predicting, for power conservation while said computer is on and processing data, said power conservation remaining transparent to a user of said computer.   
     
     
       2. The device of claim 1, including means for user modification of activity level predictions and using said modified predictions for automatic power conservation. 
     
     
       3. A device, comprising: a computer including a central processing unit (CPU);   means for sampling a utilization percentage of said central processing unit (CPU); and means for adjusting processing speed of said central processing unit (CPU) to maximize said utilization percentage.   
     
     
       4. The device of claim 3, wherein said adjustments are accomplished within central processing unit (CPU) cycles and do not affect a user's perception of performance. 
     
     
       5. The device of claim 3, wherein said means for adjusting processing speed will effect a quick slow down of the central processing unit (CPU) when an operator for third party software of the operating system/BIOS is not using the computer, thereby reducing the power consumption, and will promptly restore full CPU operation when needed without affecting perceived performance. 
     
     
       6. The device of claim 3, wherein said means for adjusting processing speed will effect a quick turn off of the central processing unit (CPU) when an operator for third party software of the operating system/BIOS is not using the computer, thereby reducing the power consumption, and will promptly restore full CPU operation when needed without affecting perceived performance. 
     
     
       7. The device of claim 6, wherein the switching back into full operation from the "slow down" mode occurs without the user having to request it and without any delay in the operation of the computer while waiting for the computer to return to a "ready" state. 
     
     
       8. A device, comprising: a central processing unit (CPU) coupled to a clock;   means for sampling activity in said central processing unit; and   means, responsive to said sampled activity, for controlling periods of time said clock is in an OFF state, the length of said periods of time said clock is in an OFF state being appropriate to allow said central processing unit to operate at a maximized utilization percentage.   
     
     
       9. The device of claim 8, wherein energy consumption in said device is at a maximum when the length of each period of time said clock is in an OFF state is at zero. 
     
     
       10. The device of claim 8, wherein energy consumption in said device decreases as the length of each period of time said clock is in an OFF state increases. 
     
     
       11. The device of claim 8, wherein said periods of time said clock is in an OFF state are constantly being adjusted to maximize said utilization percentage of said central processing unit. 
     
     
       12. The device of claim 8, wherein said OFF states represents the minimum clock rate at which said central processing unit can operate. 
     
     
       13. The device of claim 12, wherein said minimum clock rate may be zero for central processing units that can have their clocks stopped.