Communication interface between two finite state machines operating at different clock domains

Abstract

A system for creating a communication interface between a first finite state machine, operating in accordance with a write side clock in a write side clock domain, the first finite state machine operating to generate a Request signal for a transaction and for requesting the transfer of information associated with the Request signal, and a second finite state machine, operating in accordance with a read side clock in a read side clock domain at a different frequency than the write side clock, comprising: a register file; a first interface to the first finite state machine; a second interface to the second finite state machine; and logic for loading in accordance with the write side clock, a communication queue of the information into the register file in accordance with the Request signals from the first finite state machine, for reading by the second finite state machine via the second interface in accordance with the read side clock.

What is claimed is: 
     
       1. A system for creating a communication interface between a first finite state machine, operating in accordance with a write side clock domain, said first finite state machine operating to generate a Request signal for a transaction and for requesting the transfer of information associated with said Request signal, and a second finite state machine, operating in accordance with a read side clock in a read side clock domain at a different frequency than said write side clock, comprising: a register file;   a first interface to said first finite state machine;   a second interface to said second finite state machine; and   logic for loading in accordance with said write side clock, a communication queue of said information into said register file in accordance with said Request signals from said first finite state machine, for reading by said second finite state machine via said second interface in accordance with said read side clock;   wherein said second finite state machine generates a Transaction Complete signal when said transaction associated with one of said Request signals has been completed by said second finite state machine; and   wherein the logic for loading comprises: a first handshake logic which operates to generate a first handshake signal to said first finite state machine to authorize loading said register file, until said register file is filled to a threshold capacity, without reference to said Transaction Complete signal; and   a second handshake logic which operates to provide a second handshake signal to said first finite state machine upon reception of said Transaction Complete signal.     
     
     
       2. A system as defined in claim 1, wherein said register file is a first-in-first-out register file. 
     
     
       3. A system as defined in claim 1, wherein said read side clock domain includes a bus connected to main memory. 
     
     
       4. A system as defined in claim 1, further comprising a third logic to monitor a number of Transaction Complete signals received in said write side clock domain, to compare that number in the read side clock domain to a number of Transaction Complete signals generated in said read side clock domain to obtain a difference, and preventing the register file from being read if said difference has a predetermined value compared to a second threshold. 
     
     
       5. A system as defined in claim 4, wherein said third logic comprises: a first completion pointer in said read side clock domain to receive Transaction Complete signals;   a third synchronizer for resynchronizing an output from said first completion pointer to said write side clock domain;   a second completion pointer on said write side clock domain for holding a count of increments of said first completion pointer received from said read side clock domain;   a fourth synchronizer for resynchronizing an output of said second completion pointer to said read side clock domain;   a difference logic for obtaining a difference in said read side clock domain between the output of said first completion pointer and the resynchronized output from said second completion pointer; and   a comparator for comparing said difference to said second threshold value, and if said difference has a predetermined value compared to a second threshold value, generating said signal to prevent said read pointer from being incremented.   
     
     
       6. A system as defined in claim 1, wherein said first handshake logic further comprises a second logic operating in accordance with said read side clock domain for reading said register file at a location pointed to by said read pointer if an output from said write pointer is indicative that there is information to be read in said register file. 
     
     
       7. A system as defined in claim 6, wherein said second logic comprises: a second synchronizer for resynchronizing the output from said write pointer to said read side clock domain; and   a comparator in said read side clock domain for comparing the resynchronized output from said write pointer to the output from said read pointer and generating a signal to cause said register file to be read if there is a difference in values.   
     
     
       8. A system as defined in claim 6, wherein said first logic comprises: a first synchronizer for resynchronizing an output from said read pointer in accordance with said write side clock;   a difference circuit for determining a difference between the resynchronized read pointer output and the write pointer output; and   a comparison circuit for generating a signal to prevent loading of information in said register file if said difference has a predetermined value compared to said threshold value.   
     
     
       9. A system as defined in claim 1, wherein said first handshake logic generates said first handshake logic signal immediately after receipt of each Request signal until a signal indicating that said register file is filled to said threshold capacity is generated. 
     
     
       10. A system as defined in claim 9, wherein said first handshake logic comprises: a write pointer incremented upon receipt of said Request signal in accordance with said write side clock to determine which location in said register file in which to store received information;   a read pointer incremented by said second finite state machine in accordance with said read side clock to determine from which location in said register file to read information; and   a first logic for determining if said register file is at said threshold capacity based on outputs from said write pointer and said read pointer and preventing further loading of information to said register file if said register file is determined to be at said threshold capacity.   
     
     
       11. A system as defined in claim 10, wherein said first logic comprises: a first synchronizer for resynchronizing an output from said read pointer in accordance with said write side clock;   a difference circuit for determining a difference between the resynchronized read pointer output and the write pointer output; and   a comparison circuit for generating a signal to prevent loading of information in said register file if said difference has a predetermined value compared to a threshold value.   
     
     
       12. A system for creating a communication interface between a first finite state machine, operating in accordance with a write side clock domain, said first finite state machine operating to generate a Request signal for a transaction and for requesting the transfer of information associated with said Request signal, and a second finite state machine, operating in accordance with a read side clock in a read side clock domain at a different frequency than said write side clock, comprising: a register file;   a first interface to said first finite state machine;   a second interface to said second finite state machine; and   logic for loading in accordance with said write side clock, a communication queue of said information into said register file in accordance with said Request signals from said first finite state machine, for reading by said second finite state machine via said second interface in accordance with said read side clock;   wherein said second finite state machine generates a Transaction Complete signal when said transaction associated with one of said Request signals has been completed by said second finite state machine; and   further including a block complete logic for comparing in the write side clock domain the number of Request signals to the number of Transaction Complete signals received in said write side clock domain to obtain a difference and generating a Block Complete signal when said difference is zero.   
     
     
       13. An article of manufacture, comprising: a computer usable medium having computer readable code means embodied therein for controlling a chip design computer to design a circuit on a chip for creating a communication interface between a first finite state machine, operating in accordance with a write side clock in a write side clock domain and functional to generate a Request signal for a transaction and for the transfer of information associated with said Request signal, and a second finite state machine operating in accordance with a read side clock in a read side clock domain which is operating at a difference frequency than said write side clock, the computer readable code means in said article of manufacture comprising:   first computer readable code means to cause said chip design computer to design a file register; and   second computer readable code means to cause said chip design computer to design a logic for loading into said register file in accordance with said write side clock a communication queue of said information in accordance with said Request signals from said first finite state machine, for reading by said second finite state machine in accordance with said read side clock;   wherein said second finite state machine generates a Transaction Complete signal when said transaction associated with one of said Request signals has been completed by said second finite state machine; and wherein said second computer readable code means further includes third computer readable code means to cause said chip design computer to design a first handshake logic which operates to generate a first handshake signal upon receipt of each of said Request signals to authorize loading of information associated with each of said Request signals into said register file until said register file is filled to a threshold capacity, without reference to said Transaction Complete signal from said second finite state machine; and fourth computer readable code means to cause said chip design computer to design a second handshake logic which operates to provide a Transaction Complete handshake signal to said first finite state machine upon reception of each of said Transaction Complete signals.   
     
     
       14. An article of manufacture as defined in claim 13, further comprising twelfth computer readable code means to cause said chip design computer to design a block complete logic for comparing in the write side clock domain the number of Request signals to the number of Transaction Complete signals received in said write side clock domain to obtain a difference and generating a Block Complete signal when said difference is zero. 
     
     
       15. An article of manufacture, as defined in claim 13, further comprising tenth computer readable code means to cause said chip design computer to design a third logic to monitor a number of Transaction Complete signals received in said write side clock domain, to compare that number in the read side clock domain to a number of Transaction Complete signals generated in said read side clock domain to obtain a difference, and preventing the register file from being read if said difference has a predetermined value compared to a second threshold. 
     
     
       16. An article of manufacture as defined in claim 15, wherein said tenth computer readable code means includes eleventh computer readable code means to cause said chip design computer to design said third logic to include: a first completion pointer on said read side clock domain to receive Transaction Complete signals;   a third synchronizer for resynchronizing an output from said first completion pointer to said write side clock domain;   a second completion pointer on said write side clock domain for holding a count of increments of said first completion pointer received from said read side clock domain;   a fourth synchronizer for resynchronizing an output of said second completion pointer to said read side clock domain;   a difference logic for obtaining a difference in said read side clock domain between the output of said first completion pointer and the resynchronized output from said second completion pointer; and   a comparator for comparing said difference to said second threshold, and if said difference has a predetermined value compared to said second threshold, generating said signal to prevent said read pointer from being incremented.   
     
     
       17. An article of manufacture as defined in claim 13, wherein said third computer readable code means includes fifth computer readable code means to cause said chip design computer to design said first handshake logic to generate a first handshake logic signal immediately after receipt of each Request signal until a signal indicating that said register file is filled to said threshold capacity has been generated. 
     
     
       18. An article of manufacture as defined in claim 17, wherein said third computer readable code means further comprises sixth computer readable code means to cause said chip design computer to design said first handshake logic to include: a write pointer incremented upon receipt of said Request signal in accordance with said write side clock to determine which location in said register file in which to store said information;   a read pointer incremented by said read side clock to determine from which location in said register file to read information; and   a first logic for determining if said register file is at a threshold capacity based on outputs from said write pointer and said read pointer and preventing further loading of information by said register file, if said register file is determined to be at said threshold capacity.   
     
     
       19. An article of manufacture as defined in claim 18, wherein said sixth computer readable code means includes seventh computer readable code means to cause said chip design computer to design said first logic to comprise: a first synchronizer for resynchronizing an output from said read pointer in accordance with said write side clock;   a difference circuit for determining a difference between the resynchronized read pointer output and the write pointer output; and   a comparison circuit for generating a signal to prevent loading of information in said register file if said difference has a predetermined value compared to said threshold value.   
     
     
       20. An article of manufacture as defined in claim 19, wherein said third computer readable code means includes eighth computer readable code means to cause said chip design computer to design said first handshake logic to comprise a second logic operating in accordance with said read side clock domain for reading said register file at a location pointed to by said read pointer if an output from said write pointer is indicative that there is information to be read in said register file. 
     
     
       21. An article of manufacture as defined in claim 20, wherein said eighth computer readable code means include ninth computer readable code means to cause said chip design computer to design said second logic to comprise: a second synchronizer for resynchronizing the output from said write pointer to said read side clock domain; and   a comparator in said read side clock domain for comparing the resynchronized output from said write pointer to the output from said read pointer and generating a signal to cause said register to be read if there is a difference in values.   
     
     
       22. An article of manufacture as defined in claim 20, further comprising tenth computer readable code means to cause said chip design computer to design a third logic to monitor a number of Transaction Complete signals received in said write side clock domain, to compare that number in the read side clock domain to a number of Transaction Complete signals generated in said read side clock domain to obtain a difference, and preventing the register file from being read if said difference has a predetermined value compared to a second threshold. 
     
     
       23. An article of manufacture as defined in claim 22, wherein said tenth computer readable code means includes eleventh computer readable code means to cause said chip design computer to design said third logic to include: a first completion pointer on said read side clock domain, to receive Transaction Complete signals;   a third synchronizer for resynchronizing an output from said first completion pointer to said write side clock domain;   a second completion pointer on said write side clock domain for holding a count of increments of said first completion pointer received from said read side clock domain;   a fourth synchronizer for resynchronizing an output of said second completion pointer to said read side clock domain;   a difference logic for obtaining a difference in said read side clock domain between the output of said first completion pointer and the resynchronized output from said second completion pointer; and   a comparator for comparing said difference to said second threshold, and if said difference has a predetermined value compared to said second threshold, generating said signal to prevent said read pointer from being incremented.   
     
     
       24. A method for creating a communication interface between a first finite state machine, operating in accordance with a write side clock in a write side clock domain to generate a Request signal for a transaction and for requesting the transfer of information associated with said Request signal, and a second finite state machine operating in accordance with a read side clock in a read side clock domain which is operating at a different frequency than said write side clock, comprising the steps of: receiving said Request signals on said write side domain; and   storing in a communications queue said information in accordance with said Request signals, for reading by said second finite state machine in accordance with said read side clock; and further comprising the steps of: receiving a Transaction Complete signal from said second finite state machine when said second finite state machine has completed said transaction associated with one of said Request signals;   generating a first handshake signal in response to each received Request signal to thereby authorize said storing of information associated with each of said Request signals in said communication queue without reference to said Transaction Complete signals, until a signal is received indicating that said communication queue is filled to a threshold capacity; and   generating a second handshake signal to said first finite state machine upon reception of said Transaction Complete signal.     
     
     
       25. A method as defined in claim 24, further comprising the step of comparing in the write side clock domain the number of Request signals to the number of Transaction Complete signals received in said write side clock domain to obtain a difference and generating a Block Complete signal when said difference is zero. 
     
     
       26. A method as defined in claim 24, further comprising the step of monitoring a number of Transaction Complete signals received in said write side clock domain, comparing that number in the read side clock domain to a number of Transaction Complete signals generated in said read side clock domain to obtain a difference, and preventing the register file from being read if said difference has a predetermined value compared to a second threshold. 
     
     
       27. A method as defined in claim 26, wherein said Transaction Complete signal monitoring step comprises the steps of: incrementing a first completion pointer value on said read side clock domain, on receipt of each Transaction Complete signals;   resynchronizing an output of said first completion pointer value to said write side clock domain;   holding a second completion pointer value on said write side clock domain representing a count of increments of said first completion pointer value received from said write side clock domain;   resynchronizing an output of said second completion pointer value to said read side clock domain;   obtaining a difference in said read side clock domain between said first completion pointer value and the resynchronized second completion pointer value; and   comparing said difference to said second threshold, and if said difference has a predetermined value compared to said second threshold, generating said signal to prevent said read pointer from being incremented.   
     
     
       28. A method as defined in claim 24, wherein said first handshake generating signal step comprises the step of generating said first handshake signal immediately after receipt of each Request signal until said signal is received indicating that said communication queue is filled to said threshold capacity. 
     
     
       29. A method as defined in claim 28, wherein said communication queue comprises a register file; and wherein said first handshake signal generating step comprises the steps of: incrementing a write pointer upon receipt of said Request signal in accordance with said write side clock to determine which location in said register file in which to store received information;   incrementing a read pointer upon receipt of a Read Pending signal in accordance with said read side clock to determine from which location in said register file to read information; and   determining if said register file is at a threshold capacity based on outputs from said write pointer and said read pointer and preventing further loading of information by said register file, if said register file is determined to be at said threshold capacity.     
     
     
       30. A method as defined in claim 29, wherein said threshold capacity determining step comprises the steps of: resynchronizing an output from said read pointer in accordance with said write side clock;   determining a difference in said write side clock domain between the resynchronized read pointer output and the write pointer output; and   generating a signal to prevent loading of information in said register file if said difference has a predetermined value compared to a threshold value.   
     
     
       31. A method as defined in claim 30, wherein said first handshake signal generating step comprises the step of reading in accordance with said read side clock domain said register file at a location pointed to by said read pointer if an output from said write pointer is indicative that there is information to be read in said register file. 
     
     
       32. A method as defined in claim 31, wherein said reading step includes the steps of: resynchronizing the output from said write pointer to said read side clock domain; and   comparing in said read side clock domain the resynchronized output from said write pointer to the output from said read pointer and generating a signal to cause said register to be read if there is a difference in values.   
     
     
       33. A method as defined in claim 32, further comprising the step of monitoring a number of Transaction Complete signals received in said write side clock domain, comparing that number in the read side clock domain to a number of Transaction Complete signals generated in said read side clock domain to obtain a difference, and preventing the register file from being read if said difference has a predetermined value compared to a second threshold. 
     
     
       34. A method as defined in claim 33, wherein said Transaction Complete signal monitoring step comprises the steps of: incrementing a first completion pointer value on said read side clock domain, on receipt of each Transaction Complete signal;   resynchronizing an output of said first completion pointer value to said write side clock domain;   holding a second completion pointer value on said write side clock domain representing a count of increments of said first completion pointer value received from said write side clock domain;   resynchronizing an output of said second completion pointer value to said read side clock domain;   obtaining a difference in said read side clock domain between said first completion pointer value and the resynchronized second completion pointer value; and   comparing said difference to said second threshold, and if said difference has a predetermined value compared to said second threshold, generating said signal to prevent said read pointer from being incremented.