Method of fabricating bit line

Abstract

A method of fabricating a bit line comprises first that a semiconductor substrate is provided. The substrate comprises source/drain regions and a semiconductor structure. Over the substrate, an oxide layer conformal to the semiconductor substrate and a BPSG layer are formed. A contact window is formed and exposes the source/drain regions in the substrate. A polysilicon layer is formed within the contact window and connects the source/drain regions. A titanium silicide (TiSi 2 ) is formed and covers the polysilicon layer. A titanium nitride layer is formed and covers the titanium silicide layer. One of the characteristics of the invention is that a titanium silicide layer, a titanium nitride layer, and a polysilicon layer replaces the conventional tungsten silicide and the polysilicon layer to form a bit line. Therefore, the contact resistance of the bit line is reduced effectively. In addition, the titanium nitride layer can be used as a bottom anti-reflection layer to avoid the necking phenomenon while coating photoresist. Moreover, the titanium nitride layer also prevents the formation of cracking during the subsequent rapid thermal process.

What is claimed is: 
     
       1. A method of fabricating a bit line, comprising: providing a semiconductor substrate, on which a semiconductor device comprising a plurality of drain/source regions is formed;   sequentially forming an oxide layer conformal to the semiconductor device and a BPSG layer over the substrate;   forming a contact window to expose the drain/source region, using photolithography and etching;   forming a polysilicon layer contacting the exposed drain/source region;   forming a titanium silicide layer covering the polysilicon layer; and   forming titanium nitride layer covering the titanium silicide layer;   wherein the bit line consists of only the polysilicon layer, the titanium silicide layer, and the titanium nitride layer.   
     
     
       2. The method according to claim 1, wherein the semiconductor device further comprises a gate electrode, a bottom electrode, a dielectric layer, and a top electrode. 
     
     
       3. The method according to claim 2, wherein the dielectric layer is an oxide/nitride/oxide stacked layer. 
     
     
       4. The method according to claim 1, wherein forming the titanium silicide layer includes forming a titanium layer, and performing a rapid thermal process such that the titanium layer reacts with the polysilicon layer. 
     
     
       5. The method according to claim 4, wherein the titanium layer is formed by DC sputtering. 
     
     
       6. The method according to claim 1, wherein forming the titanium nitride layer includes forming a titanium layer on the titanium silicide layer, and performing a rapid thermal process in a nitrogen environment, so that the titanium layer is nitridized into the titanium nitride layer. 
     
     
       7. The method according to claim 6, wherein the titanium layer is formed by DC sputtering. 
     
     
       8. The method according to claim 1, wherein forming the titanium nitride layer includes forming a titanium layer on the titanium silicide layer, and performing a rapid thermal process in an ammonia environment, so that the titanium layer is nitridized into the titanium nitride layer. 
     
     
       9. The method according to claim 8, wherein the titanium layer is formed by DC sputtering. 
     
     
       10. The method according to claim 1, wherein the polysilicon layer has a thickness of about 1 KÅ. 
     
     
       11. The method according to claim 1, wherein the titanium silicide layer has a thickness of about 1.5 KÅ. 
     
     
       12. The method according to claim 1, wherein the titanium nitride layer has a thickness of about 300 Å. 
     
     
       13. The method according to claim 1, wherein the bit line is formed without the use of tungsten silicide.