Integrated circuit packaged for receiving another integrated circuit

Abstract

An integrated circuit combination includes a second piggy-back small integrated circuit chip mounted on the carrier of a first integrated circuit chip. The combination can be mounted on a board without requiring board space for interconnecting the first and second chips. The lid of the first chip is cut away so that the second chip can be mounted to the first without increasing the height of the combination over the height of the first chip. The two chips preferably comprise an FPGA and a PROM for programming the FPGA. The combination increases security as well as reducing board space because it is difficult to read a bitstream being transmitted from the PROM to the FPGA when the PROM is directly mounted on the FPGA.

I claim: 
     
       1. A combination of integrated circuit packages comprising: an FPGA package comprising: an FPGA chip;   a printed circuit board carrier having: a first electrical conductor extending through the printed circuit board carrier, the FPGA chip being connected to the first electrical conductor at an upper surface of the printed circuit board carrier;   a second electrical conductor extending through the printed circuit board carrier, the FPGA chip being connected to the second electrical conductor at the upper surface of the printed circuit board carrier;   a third electrical conductor extending through the printed circuit board carrier;   a fourth electrical conductor extending through the printed circuit board carrier, the FPGA chip being connected to the fourth electrical conductor at the upper surface of the printed circuit board carrier;   a first connector element connected to the second electrical conductor at a lower surface of the printed circuit board carrier, the first connector element being formed to couple the printed circuit board carrier to a printed circuit board;   a second connector element connected to the third electrical conductor at the lower surface of the printed circuit board carrier, the second connector element being formed to couple the printed circuit board carrier to the printed circuit board; and   a third connector element connected to the fourth electrical conductor at the lower surface of the printed circuit board carrier, the third connector element being formed to couple the printed circuit board carrier to the printed circuit board; and     a PROM package comprising: a PROM chip, separate from the FPGA chip, wherein the PROM chip is connected to the first electrical conductor, the third electrical conductor and the fourth electrical conductor at the upper surface of the printed circuit board carrier.       
     
     
       2. A combination of integrated circuit packages as in claim 1 wherein the PROM is programmable by passing signals through the FPGA. 
     
     
       3. A combination of integrated circuit packages as in claim 1 wherein the PROM can configure the FPGA. 
     
     
       4. A combination of integrated circuit packages as in claim 1 wherein the first electrical conductor carries a data signal. 
     
     
       5. A combination of integrated circuit packages as in claim 1 wherein the first electrical conductor is wholly contained within the printed circuit board carrier. 
     
     
       6. The combination of claim 5 wherein the first electrical conductor is dedicated for routing configuration data from the PROM chip to the FPGA chip. 
     
     
       7. An integrated circuit package comprising: a first integrated circuit chip;   a carrier having upper and lower surfaces comprising:   a first conductive line that extends through the carrier, the first integrated circuit chip being connected to the first conductive line at the upper surface of the carrier, and   a second conductive line that extends between the upper and lower surfaces of the carrier, the first integrated circuit chip being connected to the second conductive line at the upper surface of the carrier;   a third conductive line that extends between the upper and lower surfaces of the carrier;   a fourth conductive line that extends between the upper and lower surfaces of the carrier, the first integrated circuit chip being connected to the fourth conductive line at the upper surface of the carrier;   a first connector element connected to the second conductive line at the lower surface of the carrier, the first connector element being formed to connect the carrier to a printed circuit board;   a second connector element connected to the third conductive line at the lower surface of the carrier, the second connector element being formed to connect the carrier to the printed circuit board; and   a third connector element connected to the fourth conductive line at the lower surface of the carrier, the third connector element being formed to connect the carrier to the printed circuit board; and   a second integrated circuit chip separate from the first integrated circuit chip, wherein the second integrated circuit chip is connected to the first conductive line, the third conductive line, and the fourth conductive line at the upper surface of the carrier; and   a lid attached to the carrier, wherein the lid is shaped to cover the first integrated circuit chip and to leave uncovered the second integrated circuit chip.   
     
     
       8. An integrated circuit package as in claim 7 wherein the lid is at least as high as the second integrated circuit chip. 
     
     
       9. An integrated circuit package as in claim 7 wherein the first integrated circuit chip is an FPGA. 
     
     
       10. An integrated circuit package as in claim 7 wherein the first conductive line carries a data signal. 
     
     
       11. An integrated circuit package as in claim 7 wherein the first conductive line is wholly contained within the carrier. 
     
     
       12. An integrated circuit package as in claim 6 wherein the second integrated circuit chip is a PROM. 
     
     
       13. An integrated circuit package as in claim 12 wherein the PROM is programmable through the FPGA. 
     
     
       14. An integrated circuit package as in claim 12 wherein the PROM can program the FPGA. 
     
     
       15. The integrated circuit package of claim 11 wherein the first conductive line is dedicated for routing configuration data.