CMOS circuit for providing a bandcap reference voltage

Abstract

A low voltage submicron CMOS circuit (10) for providing an output bandgap voltage (V BG ) that is substantially independent of temperature and power supply variations has been provided. The CMOS circuit utilizes parasitic transistors (28-30) to create a delta voltage that has a positive temperature coefficient across a differential pair of NMOS transistors (14, 16). This delta voltage is then converted into differential currents which are amplified and mirrored and summed together to provide an output current (I O ) that has a positive temperature coefficient. This output current is then passed through a series network including a resistor element (52) and a parasitic PNP junction transistor (31) to provide a bandgap voltage of 1.2 volts wherein the voltage across the resistor element has a positive temperature coefficient and the voltage across the parasitic PNP junction transistor has an inherent negative temperature coefficient.

What is claimed is: 
     
       1. A CMOS circuit for providing a current having a positive temperature coefficient, the circuit comprising: CMOS parasitic P-N junction means for generating a delta voltage having a positive temperature coefficient;   CMOS differential amplifying means responsive to said delta voltage for providing differential currents; and   summing means responsive to said differential currents for providing a resulting current at an output of said summing means, said current having a positive temperature coefficient, and a feedback connection absent between said output of said summing means and said CMOS parasitic P-N junction means.   
     
     
       2. A method for providing an output current at an output node of a circuit manufactured using CMOS technology, the output current having a positive temperature coefficient, the method comprising the steps of: generating a delta voltage having a positive temperature coefficient without using feedback from the output node;   converting said delta voltage to differential currents;   amplifying and mirroring said differential currents; and   summing said amplified and mirrored differential currents to provide the resulting output current from the output node, said output current having a positive temperature coefficient.   
     
     
       3. A CMOS circuit for providing a bandgap reference voltage at an output that is independent of temperature, the circuit comprising: a first transistor having first and second current carrying electrodes and a control electrode;   a second transistor having first and second current carrying electrodes and a control electrode, said second current carrying electrode of said second transistor coupled to said second current carrying electrode of said first transistor;   CMOS parasitic PN junction means for generating a delta voltage between said control electrodes of said first and second transistors, said delta voltage having a positive temperature coefficient;   a current source coupled between said second current carrying electrode of said first transistor and a first supply voltage terminal;   a third transistor having first and second current carrying electrodes and a control electrode, said first current carrying electrode and said control electrode of said third transistor coupled to said first current carrying electrode of said first transistor, said second current carrying electrode of said third transistor coupled to a second supply voltage terminal;   a fourth transistor having first and second current carrying electrodes and a control electrode, said first current carrying electrode and said control electrode of said fourth transistor coupled to said first current carrying electrode of said second transistor, said second current carrying electrode of said fourth transistor coupled to said second supply voltage terminal;   a fifth transistor having first and second current carrying electrodes and a control electrode, said second current carrying electrode of said fifth transistor coupled to said second supply voltage terminal, said control electrode of said fifth transistor coupled to said first current carrying electrode of said first transistor;   a sixth transistor having first and second current carrying electrodes and a control electrode, said second current carrying electrode of said sixth transistor coupled to said second supply voltage terminal, said control electrode of said sixth transistor coupled to said first current carrying electrode of said second transistor;   a seventh transistor having first and second current carrying electrodes and a control electrode, said first current carrying and control electrodes of said seventh transistor coupled to said first current electrode of said fifth transistor, said second current carrying electrode of said seventh transistor coupled to said first supply voltage terminal;   an eighth transistor having first and second current carrying electrodes and a control electrode, said first current carrying electrode of said eighth transistor coupled to said first current electrode of said sixth transistor and to the output of the CMOS circuit, said control electrode of said eighth transistor coupled to said first current carrying electrode of said seventh transistor, said second current carrying electrode of said eighth transistor coupled to said first supply voltage terminal;   a resistor having first and second terminals, said first terminal of said resistor coupled to the output of the CMOS circuit, said resistor having a voltage appearing thereacross having a positive temperature coefficient; and   a parasitic PN junction having a negative temperature coefficient and first and second terminals, said first terminal of said parasitic PN junction coupled to said second terminal of said resistor, said second terminal of said parasitic PN junction coupled to said first supply voltage terminal.   
     
     
       4. A CMOS circuit for providing a bandgap reference voltage at an output that is independent of temperature, the circuit comprising: CMOS parasitic P-N junction means for generating a delta voltage having a positive temperature coefficient;   CMOS differential amplifying means responsive to said delta voltage for providing differential currents;   summing means responsive to said differential currents for providing a resulting current at an output of said summing means, said current having a positive temperature coefficient;   a resistor element having first and second terminals, said first terminal of said resistor element coupled to said output of said CMOS summing means, said resistor element having a voltage appearing thereacross having a positive temperature coefficient; and   a semiconductor device, the semiconductor device having a P-N junctions, a negative temperature coefficient, and first and second terminals, said first terminal of said semiconductor device coupled to said second terminal of said resistor element, said second terminal of said semiconductor device coupled to a first supply voltage terminal, said resistor element and said semiconductor device cooperating with said current having a positive temperature coefficient to provide a bandgap voltage that is substantially independent of temperature variations.   
     
     
       5. The circuit according to claim 4, wherein said resistor element is a MOS transistor such that a voltage appearing across said transistor and said semiconductor device is a bandgap voltage that is substantially independent of temperature and power supply variations, said MOS transistor having first and second current carrying electrodes and a control electrode, said first current carrying electrode coupled to said output of said CMOS summing means and serving as the first terminal of said resistor element, said second current carrying electrode coupled to said semiconductor device and serving as the second terminal of said resistor element, and said control electrode coupled to a second power supply terminal.