Thin-film transistor and liquid crystal display device

Abstract

A polysilicon pattern constituting an active portion of a TFT is formed on a substrate so as to be curved to generally assume a U shape, and a gate pattern is formed as a straight conductor pattern. The gate pattern is so disposed as to cross the U-shaped polysilicon pattern plural times. The silicon pattern comprise a plurality of channel regions and impurity regions of which alignment is symmetrical.

What is claimed is: 
     
       1. A thin-film transistor comprising: a semiconductor pattern formed over a substrate comprising a plurality of channel regions and a plurality of first diffusion regions formed on both sides of each of said channel regions, said semiconductor pattern having at least one curved portion;   a gate pattern which is a straight conductor pattern and is placed to cross said semiconductor pattern plural times;   a source line connected with a first one of said first diffusion regions; and   a pixel electrode connected with a second one of said first diffusion regions,   wherein at least a third one of the first diffusion regions is disposed between said first one and second one of the first diffusion regions,   wherein said semiconductor pattern further comprises, between each channel region and each first diffusion region, a plurality of second diffusion regions having a lower impurity concentration than said first diffusion regions,   wherein two of said second diffusion regions, which are contiguous to said first and second ones of the first diffusion regions, respectively, have a same width, and   wherein said width of said two second diffusion regions is larger than widths of others of the second diffusion regions.   
     
     
       2. A thin-film transistor according to claim 1, wherein said semiconductor pattern is formed in a U shape. 
     
     
       3. A thin-film transistor according to claim 1, wherein said semiconductor pattern comprises crystalline silicon. 
     
     
       4. A thin-film transistor according to claim 1 wherein said plurality of first diffusion regions are impurity regions and said plurality of second diffusion regions are LDD regions. 
     
     
       5. A thin-film transistor according to claim 1 wherein an arrangement of said channel, first diffusion, and second diffusion regions in said semiconductor pattern is symmetrical. 
     
     
       6. A semiconductor device comprising: a plurality of thin-film transistors arranged on a substrate in matrix form, each of the thin-film transistors comprising: a semiconductor pattern formed over a substrate comprising a plurality of channel regions, a plurality of impurity regions, and a plurality of LDD regions, each of said impurity regions disposed adjacent to one of said channel regions with one of said LDD regions interposed therebetween, said semiconductor pattern having at least one curved portion;   a gate pattern which is straight conductor pattern arranged to cross said semiconductor pattern plural times;   a source line connected with a first one of said impurity regions; and   a pixel electrode connected with a second one of said impurity regions,   wherein at least a third one of said impurity region is disposed between said first one and second one of the impurity regions, and   wherein two of the LDD regions which are contiguous to said first and second ones of the impurity regions, respectively, are a same width different from others of the LDD regions in the semiconductor pattern.     
     
     
       7. A device according to claim 6, further comprising a straight light-interrupting pattern extending to cover throughout said gate pattern and said plurality of LDD regions. 
     
     
       8. A semiconductor device comprising: a plurality of thin-film transistors arranged on a substrate in matrix form, each of the thin-film transistors comprising: a semiconductor pattern comprising crystalline silicon formed over a substrate comprising a plurality of channel regions, a plurality of first diffusion regions formed on both sides of each of said channel regions, and a plurality of second diffusion regions having a lower impurity concentration than said first diffusion regions, each second diffusion region formed between one of said channel region and one of said first diffusion region, said semiconductor pattern having at least one curved portion;   a gate pattern which is a straight conductor pattern arranged to cross said semiconductor pattern plural times;   a data pattern connected with a first one of said first diffusion regions;   a pixel electrode connected with a second one of said first diffusion regions; and   a straight light-interrupting pattern extending to cover throughout said gate pattern and said plurality of second diffusion regions,   wherein said data pattern and said gate and straight light-interrupting patterns cross at right angles, and   wherein two of the second diffusion regions, one contiguous to said first one of the first diffusion regions and one contiguous to said second one of the first diffusion regions, respectively, have a same width different from widths of others of the second diffusion regions in the semiconductor pattern.     
     
     
       9. A device according to claim 8 wherein an arrangement of said channel, first diffusion, and second diffusion regions in said semiconductor pattern is symmetrical. 
     
     
       10. A device according to claim 8, wherein the width of said two of the second diffusion regions is larger than widths of others of the second diffusion regions. 
     
     
       11. A device according to claim 8, wherein said semiconductor pattern comprises crystalline silicon. 
     
     
       12. A device according to claim 8, wherein said semiconductor pattern is formed in a U shape. 
     
     
       13. A device according to claim 6, wherein said gate pattern comprises aluminum. 
     
     
       14. A device according to claim 6, wherein said semiconductor pattern is formed in a U shape.