System and method for interfacing a digital signal processor (DSP) to an audio bus containing frames with synchronization data

Abstract

An audio bus interface system and method interfaces a plurality of digital signal processing devices to an audio bus to facilitate variable processing loading on the DSPs. The audio bus contains frames with synchronization data. The system utilizes a programmable interrupt controller for each digital signal processing unit. The programmable interrupt controller controls the rate at which a given DSP can be interrupted. The respective digital signal processor controls the programmable interrupt controller to maximize its throughput. Also, an audio format translator allows differing audio format protocols to be processed by the same audio DSP.

What is claimed is: 
     
       1. An audio bus interface for interfacing a first digital signal processor (DSP) to an audio bus containing frames with synchronization data therein comprising: means for generating first variable interrupt interval control data; and   means, responsive to the synchronization data, for programmably varying interrupt intervals for the digital signal processor in response to the first variable interrupt interval control data to facilitate variable processing loading on the DSP.   
     
     
       2. The audio bus interface of claim 1 wherein the means for programmably varying interrupt intervals includes means, responsive to the synchronization data, for counting a number of synchronization pulses and means, responsive to the first variable interrupt interval control data, for setting an interrupt interval threshold and means for comparing the counted number of synchronization pulses to the first variable interrupt interval control data to determine a variable interrupt interval. 
     
     
       3. The audio bus interface of claim 1 further including bus protocol format translation means for facilitating audio protocol format translation between differing audio data protocols over the same audio bus. 
     
     
       4. The audio bus interface of claim 1 including: audio bus interface FIFO buffer means for storing audio data from the audio bus, coupled between the DSP and the audio bus; and   means, readable by the DSP, for storing status data representing a status of the audio bus interface FIFO buffer means to facilitate transfer of information to and from the audio bus interface FIFO buffer means.   
     
     
       5. The audio bus interface of claim 4 wherein the audio bus interface FIFO buffer means includes single port FIFO storage elements to facilitate resynchronization of a DSP clock domain with a clock domain of the audio bus. 
     
     
       6. The audio bus interface of claim 4 wherein the audio bus transfers audio for a plurality of audio streams and the audio bus interface FIFO buffer means includes a transmit and receive storage element for each of the plurality of audio streams that is readable by the DSP. 
     
     
       7. The audio bus interface of claim 1 wherein the audio bus transfers data to a second DSP and the means for generating variable interrupt interval control data generates second variable interrupt interval control data for the second DSP and the means for programmably varying interrupt intervals varies an interrupt interval for the second DSP in response to the second variable interrupt interval control data. 
     
     
       8. The audio bus interface of claim 7 wherein the means for programmably varying interrupt intervals is also operably coupled to the second DSP and further includes means, responsive to the synchronization data, for counting a number of synchronization pulses for the second DSP and means, responsive to the second variable interrupt interval control data for setting an interrupt interval threshold for the second DSP and means for comparing the counted number of synchronization pulses to the second variable interrupt interval control data to determine an interrupt interval for the second DSP. 
     
     
       9. An audio bus interface for interfacing a first and a second digital signal processor (DSP) to an audio bus containing frames with synchronization data therein comprising: means for dynamically programming interrupt intervals for the first and second DSP to facilitate first and second DSP bandwidth usage enhancement which includes: means for generating first variable interrupt interval control data; and   means, responsive to the synchronization data, for programmably varying interrupt intervals for the first digital signal processor in response to the first variable interrupt interval control data to facilitate variable processing loading on the first DSP; and     interface FIFO means, operatively coupled between the first DSP and the audio bus, for storing a plurality of differing data streams transferred over the audio bus wherein the interface FIFO means includes a dedicated transmit and receive storage element for each of a plurality of audio streams sent on the audio bus.   
     
     
       10. The audio bus interface of claim 9 wherein the first DSP processes real time pulse code modulated audio data and the second DSP processes modem data. 
     
     
       11. The audio bus interface of claim 9 including means, readable by the first DSP, for storing status data representing a status of each of the dedicated transmit and receive storage elements to facilitate transfer of information to and from the interface FIFO means. 
     
     
       12. A method for interfacing a digital signal processor (DSP) to an audio bus containing frames with synchronization data therein comprising: generating first variable interrupt interval control data; and   programmably varying interrupt intervals for the digital signal processor in response to the first variable interrupt interval control data to facilitate variable processing loading on the DSP.   
     
     
       13. The method for interfacing of claim 12 wherein the step of programmably varying interrupt intervals include counting a number of synchronization pulses, setting an interrupt interval threshold and comparing the counted number of synchronization pulses to the variable interrupt interval control data to determine an interrupt interval. 
     
     
       14. The method for interfacing of claim 12 further including the step of providing bus protocol format translation for facilitating bus protocol format translation between differing protocols over the same audio bus. 
     
     
       15. The method for interfacing of claim 12 including: storing audio data from the audio bus in an audio bus interface FIFO buffer that is coupled between the DSP and the audio bus; and   storing status data representing a status of the audio bus interface FIFO to facilitate transfer of information to and from the audio bus interface FIFO buffer.   
     
     
       16. The method for interfacing of claim 15 wherein the audio bus interface FIFO buffer is a single port FIFO storage element to facilitate resynchronization of a DSP clock domain with a clock domain of the audio bus. 
     
     
       17. The method for interfacing of claim 15 wherein the audio bus transfers audio for a plurality of audio streams and the audio bus interface FIFO buffer means includes a transmit and receive storage element for each of the plurality of audio streams that is readable by the DSP. 
     
     
       18. The method for interfacing of claim 12 wherein the audio bus transfers data to another DSP and wherein generating variable interrupt interval control data includes generating second variable interrupt interval control data for the other DSP and the step of programmably varying interrupt intervals includes varying an interrupt interval for the other DSP in response to the second variable interrupt interval control data. 
     
     
       19. The method for interfacing of claim 18 wherein the step of programmably varying interrupt intervals includes counting a number of synchronization pulses for another DSP and setting an interrupt interval threshold for the other DSP in response to second variable interrupt interval control data and comparing the counted number of synchronization pulses to the second variable interrupt interval control data to determine an interrupt interval for the other DSP.