Microcontroller having register direct and register indirect addressing

Abstract

A microprocessor on-board RAM provides both the usual random access by addressing and a subset of memory cells with their contents continually available on a secondary bus paralleling the data bus. This secondary bus may be used for register indirect addressing without a separate register read when the RAM subset includes the registers for register indirect addressing. The processor also has a two stage output driver for limiting maximum output current and feedback-controlled clock period partitioning.

What is claimed is: 
     
       1. A micro controller capable of indirect addressing comprising: a data bus;   a memory having at least one register;   a bank select circuit coupled to said memory so as to directly couple a given one of said at least one registers to said data bus such that the contents are directly placed on said bus;   wherein the contents of a selected register is provided directly to said data bus, as an address for the completion of an instruction and wherein from the data bus to the selected one of said at least one register, is a read only path to the data bus from the register and wherein said selected at least one register has a fixed address and further wherein the contents of said at least one register directly provides the address for a byte of data which is the address for an instruction to be executed by said micro controller, such that the providing of the address occurs such that the full instruction can be completed within one clock cycle of said micro controller.   
     
     
       2. A micro controller as in claim 1 wherein said memory is organized in at least two banks and wherein each bank has at least two resisters. 
     
     
       3. A micro controller capable of indirect addressing comprising: a data bus;   a memory having at least one indirect addressing address register;   a bank select circuit coupled to said memory so as to directly couple a given one of said at least one indirect addressing address registers to said data bus such that the contents are directly placed on said bus;   wherein the contents of a selected indirect addressing address register is provided directly to said data bus, so as to supply an address for the completion of an instruction and wherein from the data bus to the selected one of said at least one indirect addressing address register, is a read only path to the data bus from the indirect addressing address register and wherein said selected at least one indirect addressing address register has a fixed address and further wherein the contents of said at least one indirect addressing address register directly provides the address for a byte of data which is the address for an instruction to be executed by said micro controller, such that the providing of the address occurs such that the full instruction can be completed within one clock cycle of said micro controller.   
     
     
       4. A micro controller as in claim 3 wherein said memory is organized in at least two banks and wherein each bank has at least two indirect addressing address registers.