Chain-latch circuit achieving stable operations

Abstract

A semiconductor integrated circuit includes a circuit including a plurality of memory blocks connected in series and operating in synchronism with a clock signal, the circuit holding data in each of the memory blocks during a data-hold state and holding the data between adjacent ones of the memory blocks during a data-transition state. The semiconductor integrated circuit further includes a memory circuit inserted between at least two adjacent ones of the memory blocks and operating in synchronism with the clock signal, the memory circuit holding the data between the at least two adjacent ones of the memory blocks during the data-transition period.

What is claimed is: 
     
       1. A semiconductor integrated circuit comprising: a chain latch circuit including a plurality of chain latch memory blocks connected in series and operating in synchronism with a clock signal, said chain latch circuit holding data in each of said chain latch memory blocks during a data-hold state and holding said data between adjacent ones of said chain latch memory blocks during a data-transition state; and   a memory circuit inserted between at least two adjacent ones of said chain latch memory blocks and operating in synchronism with said clock signal, said memory circuit holding said data between said at least two adjacent ones of said chain latch memory blocks during said data-transition period.   
     
     
       2. The semiconductor integrated circuit as claimed in claim 1, wherein said memory circuit comprises a flip flop. 
     
     
       3. A semiconductor integrated circuit comprising: a chain latch circuit including a plurality of chain latch memory blocks connected in series and operating in synchronism with a clock signal, said chain latch circuit holding data in each of said chain latch memory blocks during a data-hold state and holding said data between adjacent ones of said chain latch memory blocks during a data-transition state; and   a data-hold circuit attached to at least one of said chain latch memory blocks and serving as an external support to hold data which is held by said at least one of said chain latch memory blocks during said data-hold state.   
     
     
       4. The semiconductor integrated circuit as claimed in claim 3, further comprising a connection-control circuit which controls a signal connection between said data-hold circuit and said at least one of said chain latch memory blocks. 
     
     
       5. The semiconductor integrated circuit as claimed in claim 4, wherein said connection-control circuit controls said signal connection in synchronism with said clock signal. 
     
     
       6. The semiconductor integrated circuit as claimed in claim 4, wherein said connection-control circuit controls said signal connection in synchronism with another clock signal having a timing ahead of a timing of said clock signal. 
     
     
       7. The semiconductor integrated circuit as claimed in claim 4, wherein said connection-control circuit comprises transmission gates. 
     
     
       8. The semiconductor integrated circuit as claimed in claim 3, wherein said data-hold circuit comprises a latch circuit. 
     
     
       9. The semiconductor integrated circuit as claimed in claim 3, wherein said data-hold circuit comprises a latch-amplifier circuit.