Calibration sharing for CMOS output driver

Abstract

A circuit for matching the impedance of a first array of transistors to an external resistor is used to produce a first set of control signals. This first set of control signals is used to control another array of transistors to replicate the impedance of the first array of transistors. This replicated impedance is then used by another circuit for matching impedance to produce a second set of control signals that control an array of transistor of a different type to match the impedance of the first two array. The two sets of control signals may then be used as calibration signals for the pull-up and pull-down transistors of multiple output drivers.

What is claimed is: 
     
       1. A calibration circuit, comprising: a first set of calibration signals generated by a first feedback system;   a second set of calibration signals generated by a second feedback system;   a first transistor array wherein said first transistor array is controlled by said first set of calibration signals to match the impedance of a first resistor; and,   a second transistor array wherein said second transistor array is controlled by said second set of calibration signals to match the impedance of a third transistor array wherein said third transistor array is controlled by said first set of calibration signals.   
     
     
       2. The calibration circuit of claim 1, wherein said third transistor array is sized such that when said third transistor array is controlled by said first set of calibration signals the impedance of said third transistor array nearly matches the impedance of said first resistor. 
     
     
       3. The calibration circuit of claim 2 wherein said first feedback system comprises: a first voltage divider comprised of said first transistor array and said first resistor;   a first comparator wherein said first comparator compares a first divided node of said first voltage divider with a first reference voltage to produce a first comparator output; and,   a first up/down counter wherein said first up/down counter counts a first binary output up and down according to said first comparator output and said first binary output is coupled to said first set of calibration signals.   
     
     
       4. The calibration circuit of claim 3 wherein said second feedback system comprises: a second voltage divider comprised of said second transistor array and said third transistor array;   a second comparator wherein said second comparator compares a second divided node of said second voltage divider with a second reference voltage to produce a second comparator output; and,   a second up/down counter wherein said second up/down counter counts a second binary output up and down according to said second comparator output and said second binary output is coupled to said second set of calibration signals.   
     
     
       5. The calibration circuit of claim 4 wherein said first transistor array is comprised of PFETs and wherein said second transistor array is comprised of NFETs and wherein said third transistor array is comprised of PFETs. 
     
     
       6. A method of producing a first set of calibration signals and a second set of calibration signals, comprising: producing said first set of calibration signals that control a first transistor array to match the impedance of a first resistor;   producing said second set of calibration signals that control a second transistor array to match the impedance of a third transistor array; and,   applying said first set of calibration signals to said third transistor array to control said third transistor array to match the impedence of said first transistor array.   
     
     
       7. The method of claim 6 wherein said first transistor array is comprised of PFETs and wherein said second transistor array is comprised of NFETs and wherein said third transistor array is comprised of PFETs. 
     
     
       8. A calibration circuit, comprising: a first feedback system producing a first set of calibration signals that control a first transistor array to match the impedance of a resistor;   a second feedback system producing a second set of calibration signals that control a second transistor array to match a multiple of the impedance of said first transistor array.   
     
     
       9. The calibration circuit of claim 8, further comprising: a third transistor array controlled by said first set of calibration signals that is used by said second feedback system to replicate the impedance of said first transistor array.   
     
     
       10. The calibration circuit of claim 9, wherein said second feedback system uses said second transistor array and said third transistor array in a voltage divider to test whether the impedance of said second transistor array nearly matches the impedance of said third transistor array.