Driving circuit and method thereof for a display device

Abstract

A driving circuit for an electric charge recycling TFT-LCD and a method thereof which are capable of preventing a characteristic deterioration of an LCD and TFT by reducing a power consumption of a dot inversion and column inversion methods. The circuit includes a connector unit, e.g., a recycling unit, having a plurality of transmission gates and/or pass transistors connected between the data driving unit and the LCD panel, that recycles electric charges charged in the data line DL in accordance with an electric charge recycling control signal CR during a blank time.

What is claimed is: 
     
       1. A display device comprising: a first driving circuit coupled to first signal lines;   a second driving circuit coupled to second signal lines;   a display unit having a plurality of pixels, each pixel coupled to a corresponding first signal line and a corresponding second signal line; and   a connector unit coupled to said first driving circuit and the first signal lines, said connector unit connecting corresponding first signal lines to each other for a prescribed period of time, wherein said connector unit connects adjacent odd and even first signal lines said connector unit is a recycling unit which recycles charges on the first signal lines during connection of the adjacent odd and even first signal lines.   
     
     
       2. The display device of claim 1, wherein said display unit is a liquid crystal display panel. 
     
     
       3. The display device of claim 2, wherein each pixel comprises a transistor having first and second electrodes and a control electrode, a first capacitor and a second capacitor, said first and second capacitors being coupled to the second electrode. 
     
     
       4. The display device of claim 3, wherein said first driving circuit is a data driving unit and the first signal lines are data lines, a corresponding data line being coupled to the first electrode of a corresponding transistor of the pixel. 
     
     
       5. The display device of claim 4, wherein said second driving circuit is a gate driving unit and the second signal lines are gate lines, a corresponding gate line being coupled to the control electrode of the corresponding transistor of the pixel. 
     
     
       6. The display device of claim 1, wherein said recycling unit couples adjacent odd and even first signal lines having opposite signal polarity compared to a median voltage level. 
     
     
       7. The display device of claim 6, wherein said recycling unit comprises at least one of a plurality of transmission gates and a plurality of pass transistors, each of said at least one of said plurality of transmission gates and said plurality of pass transistors being connected to adjacent odd and even signal lines and being responsive to a control signal to short circuit adjacent odd and even signal lines. 
     
     
       8. The display device of claim 7, wherein the control signal activates at least one of said plurality of transmission gates and said plurality of pass transistors for the prescribed period of time in between applications of signals on the adjacent odd and even first signal lines. 
     
     
       9. The display device of claim 8, wherein the control signal activates at least one of said plurality of transmission gates and said plurality of pass transistors for the prescribed period of time during horizontal blank times. 
     
     
       10. The display device of claim 8, wherein the control signal activates at least one of said plurality of transmission gates and said plurality of pass transistors for the prescribed period of time during vertical blank times. 
     
     
       11. The display device of claim 1, wherein said connector unit is a recycling unit that short circuits adjacent odd and even first signal lines having opposite signal polarity relative to a median voltage level in response to a control signal of a prescribed level applied for the prescribed period of time. 
     
     
       12. The display device of claim 1, wherein said connector unit connects adjacent odd and even first signal lines for the prescribe period of time in between application of signals on the corresponding first signal lines. 
     
     
       13. The display device of claim 12, wherein the prescribed period of time occurs during horizontal blank times. 
     
     
       14. The display device of claim 12, wherein the prescribed period of time occurs during vertical blank times. 
     
     
       15. A recycling unit for a display device having a plurality of pixels coupled to a plurality of first and second signal lines, comprising: at least one of a plurality of transmission gates and a plurality of pass transistors, each of said at least one of said plurality of transmission gates and said plurality of pass transistors being connected to corresponding adjacent odd and even first signal lines having opposite signal polarity compared to a median potential level and being responsive to a control signal to short circuit the corresponding adjacent odd and even first signal lines for a prescribed period of time in between application of signals of opposite polarity.   
     
     
       16. The recycling unit of claim 15, wherein the first and second signal lines are data and gate lines, respectively. 
     
     
       17. The recycling unit of claim 15, the corresponding first signal lines are adjacent odd and even first signal lines. 
     
     
       18. The recycling unit of claim 15, wherein the prescribed period of time is one of horizontal blank time and vertical blank time. 
     
     
       19. A method of driving a display device having a plurality of pixels coupled to a plurality of first and second signal lines, the method comprising the steps of: applying first signals of opposite polarity relative to a median potential level to corresponding first signal lines;   applying a second signal to the plurality of second signal lines in a prescribed sequence; and   short circuiting corresponding adjacent odd and even first signal lines having first signals of opposite polarity for a prescribed period of time in between application of first signals such that charges between corresponding adjacent odd and even first signal lines are recycled.   
     
     
       20. The method of claim 19, wherein the first and second signal lines are data and gate lines, respectively. 
     
     
       21. The method of claim 19, the corresponding first signal lines are adjacent odd and even first signal lines. 
     
     
       22. The method of claim 19, wherein the prescribed period of time is one of horizontal blank time and vertical blank time.