Information processing device and method for sequence control and data processing

Abstract

An information processing device includes a general-purpose personal computer 200, and a sequence engine 300 having a rudder interpreter 301 connected to the general-purpose personal computer 200 through a personal computer expansion bus 500. The rudder interpreter 301 executes a sequence instruction based on a predetermined sequence program in accordance with an instruction sent from the general-purpose personal computer 200. The general-purpose personal computer 200 performs information processing based on a predetermined information processing program, and executes peripheral processing in accordance with a peripheral processing request sent from the rudder interpreter 301.

We claim: 
     
       1. A sequence control device comprising a data processing device provided with a processor and an internal bus connected to said processor, and sequence instruction execution means connected to said internal bus, wherein said data processing device or said sequence instruction execution means includes a user memory for storing a sequence program prepared by a user and an I/O memory for storing a status of input/output, and   an I/O board connected to an external device controlled by an instruction of said sequence program that is connected independently of said sequence instruction execution means to said internal bus.   
     
     
       2. A sequence control device comprising a data processing device provided with a processor and an internal bus connected to said processor, and sequence instruction execution means connected to said internal bus, wherein said data processing device or said sequence instruction execution means includes a user memory for storing a sequence program prepared by a user and an I/O memory for storing a state of input/output,   an I/O board having memory means and connected to an external device is connected independently of said sequence instruction execution means to said internal bus, and   said data processing device includes processing execution means for executing predetermined peripheral processing after interpretation and execution of an instruction in said user memory by said sequence instruction execution means.   
     
     
       3. The sequence control device according to claim 2, wherein said processing execution means includes: information processing execution means for executing information processing based on a predetermined information processing program,   processing interruption control means for controlling interruption of the information processing executed by said information processing execution means,   determining means for determining presence or absence of a peripheral processing request issued from said sequence instruction execution means upon interruption of the information processing by said processing interruption control means,   peripheral processing execution means for executing said peripheral processing when said determining means determines the presence of the peripheral processing request issued from said sequence instruction execution means, and   processing restart control means for controlling restart of the information processing interrupted by said processing interruption control means.     
     
     
       4. The sequence control device according to claim 3, wherein said information processing program is formed of a plurality of blocks, and   said information processing execution means executes the information processing a block at a time.   
     
     
       5. The sequence control device according to claim 4, wherein said determining means determines the presence or absence of the peripheral processing request issued from said sequence instruction execution means upon every completion of said information processing performed a block at a time.   
     
     
       6. The sequence control device according to claim 2, wherein said sequence program is formed of a ladder program, and   said sequence instruction execution means includes a ladder interpreter performing instruction execution processing by interpreting and executing said ladder program.   
     
     
       7. The sequence control device according to claim 6, wherein said sequence instruction execution means includes register means for managing the instruction execution processing by said ladder interpreter.   
     
     
       8. The sequence control device according to claim 7, wherein said register means includes: a program counter register having a value to be initially set upon start-up of said ladder interpreter and incremented upon every execution of one instruction of said ladder program,   a status register storing a status of execution of the ladder program by said ladder interpreter, and   an address register storing a leading address of the ladder program executed by said ladder interpreter.     
     
     
       9. The sequence control device according to claim 8, wherein said status register stores a start flag indicating start and stop of said ladder interpreter.   
     
     
       10. The sequence control device according to claim 9, wherein said ladder interpreter performs said instruction execution processing based on the leading address stored in said address register when said start flag indicates start-up of said ladder interpreter, and requests said data processing device to perform said peripheral processing when said start flag indicates stop of said ladder interpreter.   
     
     
       11. The sequence control device according to claim 9, wherein said start flag is written into said status register based on an instruction issued from said data processing device.   
     
     
       12. The sequence control device according to claim 2, further comprising: sequence program execution support means for executing a sequence program stored in said user memory instead of said sequence instruction execution means.   
     
     
       13. The sequence control device according to claim 8, wherein said status register stores a first flag indicating start and stop of said ladder interpreter, and a second flag indicating whether said instruction execution processing by said ladder interpreter is to be requested to said data processing device or not.   
     
     
       14. The sequence control device according to claim 13, wherein said ladder interpreter executes said instruction execution processing based on the leading address stored in said address register, when said first flag indicates start-up of said ladder interpreter and said second flag does not indicate a request to said data processing device for said instruction execution processing; requests said data processing device to perform said instruction execution processing when said first flag indicates start-up of said ladder interpreter and said second flag indicates a request to said data processing device for said instruction execution processing; and requests said data processing device to perform peripheral processing such as refreshing of the I/O port when said start flag indicates stop of said ladder interpreter and said second flag does not indicate a request to said data processing device for said instruction execution processing.   
     
     
       15. The sequence control device according to claim 13, wherein a process is determined as an error and processing for an error is executed in such a case, during said instruction execution processing by said ladder interpreter, that said first flag indicates stop of said ladder interpreter and said second flag indicates a request to said data processing device for said instruction execution processing; in such cases, during said instruction execution processing by said data processing device, that said first flag indicates start-up of said ladder interpreter and said second flag indicates a request to said data processing device for said instruction execution processing, that said first flag indicates stop of said ladder interpreter and said second flag indicates a request to said data processing device for said instruction execution processing, and that said start flag indicates stop of said ladder interpreter and said second flag does not indicate a request to said data processing device for said instruction execution processing; and in such cases, during said peripheral processing by said data processing device, that said first flag indicates start-up of said ladder interpreter and said second flag indicates a request to said data processing device for said instruction execution processing, and that said first flag indicates stop of said ladder interpreter and said second flag indicates a request to said data processing device for said instruction execution processing.   
     
     
       16. The sequence control device according to claim 13, wherein said first and second flags are written into said status register based on an instruction issued from said data processing device.   
     
     
       17. A sequence control method comprising the step of: connecting a sequence instruction execution unit to a data processing device through a bus, wherein said sequence instruction execution unit executes a sequence instruction based on a predetermined sequence program in response to an instruction issued from said data processing device, and   said data processing device performs information processing based on a predetermined information processing program, and executes peripheral processing in accordance with a peripheral processing request issued from said sequence instruction execution unit.     
     
     
       18. The sequence control method according to claim 17, wherein said data processing device: determines presence or absence of the peripheral processing request issued from said sequence instruction execution unit during information processing based on a predetermined information processing program,   interrupts said information processing to execute the peripheral processing when it is determined that the peripheral processing request issued from said sequence instruction execution unit is present, and   restarts said information processing after completion of said peripheral processing.   
     
     
       19. The sequence control method according to claim 17, wherein said information processing program is formed of a plurality of blocks,   said data processing device determines presence or absence of the peripheral processing request issued from said sequence instruction execution unit upon every completion of information processing performed a block at a time,   said information processing is interrupted and said peripheral processing is executed when it is determined that the peripheral processing request issued from said sequence instruction execution unit is present, and   said information processing is restarted after completion of said peripheral processing.   
     
     
       20. The sequence control method according to claim 19, wherein internal contents of the interrupted information processing are saved upon interruption of said information processing, and   restart of said information processing is performed based on the saved internal contents of said information processing.   
     
     
       21. The sequence control method according to claim 17, wherein said sequence program is formed of a ladder program, and   said sequence instruction execution unit executes said ladder program by interpreting said ladder program.   
     
     
       22. A sequence control method comprising the steps of: connecting a sequence instruction execution unit to a data processing device through a bus, and storing a sequence program in said data processing device, wherein said sequence instruction execution unit executes said sequence program by accessing through said bus said sequence program stored in said data processing device based on an instruction issued from said data processing device.     
     
     
       23. A sequence control method comprising the steps of: connecting sequence instruction execution unit to a data processing device through a bus, and storing a sequence program in said data processing device,   wherein said sequence instruction execution unit either executes said sequence program by accessing, through said bus, said sequence program stored in said data processing device based on an instruction issued from said data processing device, or said sequence instruction execution unit requests said data processing device to execute said sequence program in accordance with an instruction issued from said data processing device, and restarts execution by said sequence execution instruction unit when the requested execution of said sequence program by said data processing device is completed.   
     
     
       24. The sequence control method according to claim 22, wherein said sequence instruction execution unit finishes execution of said sequence program, and requests said data processing device to execute a peripheral processing in accordance with an instruction issued from said data processing device.   
     
     
       25. The sequence control method according to claim 22, wherein said sequence instruction execution unit is provided with a register for managing execution of said sequence program,   a start flag indicating start and stop of said sequence instruction execution unit is written into said register in accordance with an instruction issued from said data processing device, and   start and stop of said data processing device are controlled with reference to said written start flag.   
     
     
       26. The sequence control method according to claim 22, wherein said sequence instruction execution unit is provided with a register for managing execution of said sequence program,   a start flag indicating start and stop of said sequence instruction execution unit and a second flag indicating whether said data processing device is to be requested to perform the instruction execution processing to be performed by said sequence instruction execution unit are written into said register in accordance with an instruction issued from said data processing device, and   start and stop of said data processing device and requests to said data processing device for the instruction execution processing and the peripheral processing are controlled with reference to said written first and second flags.   
     
     
       27. A sequence engine comprising: a ladder interpreter connected to an internal bus of a data processing device, and started up by said data processing device for executing a ladder instruction by interpreting said ladder instruction; and   a register for managing and storing a status of execution of a ladder program by said ladder interpreter, wherein said sequence engine does not have a function of executing peripheral processing.     
     
     
       28. A storage medium applied to an sequence control device, wherein said sequence control device includes: a data processing device having a processor and an internal bus connected to said processor,   a sequence instruction execution unit connected to said internal bus,   a user memory for storing a sequence program and an I/O memory for storing a status of input/output, said user memory and said I/O memory being provided at said data processing device or said sequence instruction execution unit, and   an I/O board connected to an external device controlled by an instruction of said sequence program, and connected independently of said sequence instruction execution unit to said internal bus; and     wherein said storage medium stores a program for executing peripheral processing by said data processing device, said peripheral processing including I/O refreshing performed by storing data supplied from said external device and stored in a storage unit of said I/O board in said I/O memory after interpretation and execution of the instruction in said user memory by said sequence instruction execution unit, and by outputting the data in said I/O memory to said external device through said I/O board.